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INTERRUPTS
Interrupts can be enabled and disabled quickly by the new
take four cycles each to execute.
interrupt enable value. See
information on these instructions.
11.7.5.3
Default and Reset Register Values
The ICON and IMAP2:0 control registers are loaded from the control table in external memory
when the processor is initialized or reinitialized. The control table is described in
"Control Table" (pg.
12-20). The IMSK register is set to 0 when the processor is initialized
(RESET is deasserted). The IPND register value is undefined after a power-up initialization (cold
reset). The application is responsible for clearing this register before any mask register bits are set;
otherwise, unwanted interrupts may be triggered. The pending register value is retained for a reset
while power is on (warm reset).
11.8
INTERRUPT OPERATION SEQUENCE
The interrupt controller, microcode and core resources handle all stages of interrupt service.
Interrupt service is handled in the following stages:
Requesting Interrupt — In the i960 Jx processor, the programmable on-chip interrupt controller
transparently manages all interrupt requests. Interrupts are generated by hardware (external
events) or software (the application program). Hardware requests are signaled on the 8-bit external
interrupt port (XINT[7:0]), the non-maskable interrupt pin (NMI) or the two timer channels.
Software interrupts are signaled with the
Posting Interrupts — When an interrupt is requested, the interrupt is either serviced immediately
or saved for later service, depending on the interrupt's priority. Saving the interrupt for later
service is referred to as posting. Once posted, an interrupt becomes a pending interrupt. Hardware
and software interrupts are posted differently:
•
Hardware interrupts are posted by setting the interrupt's assigned bit in the interrupt pending
(IPND) memory mapped register
•
Software interrupts are posted by setting the interrupt's assigned bit in the interrupt table's
pending priorities and pending interrupts fields
11-28
takes a few cycles longer because it returns the previous
intctl
CHAPTER 6, INSTRUCTION SET REFERENCE
instruction with post-interrupt message type.
sysctl
intdis
and
inten
instructions, which
section 12.3.3,
for more
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