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EXTERNAL BUS
14.2.7
Atomic Bus Transactions
The atomic instructions,
, consist of a load and store request to the same memory
atadd and atmod
location. Atomic instructions require indivisible, read-modify-write access to memory. That is,
another bus agent must not access the target of the atomic instruction between read and write
cycles. Atomic instructions are necessary to implement software semaphores.
For atomic bus accesses, the 80960Jx processor asserts the LOCK pin during the first Ta of the
read operation and deasserts LOCK in the last data transfer of the write operation. LOCK is
deasserted at the same clock edge that BLAST is asserted. The i960Jx processor does not assert
LOCK except while a read-modify-write operation is in progress. While LOCK is asserted, the
processor can perform other, non-atomic, accesses such as fetches. However, the 80960Jx
processor will not acknowledge HOLD requests. This behavior is an enhancement over earlier
i960 microprocessors.
Figure 14-17
illustrates locked read/write accesses associated with an
atomic instruction.
14-30
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