Intel i960 Jx Developer's Manual page 18

Figure 11-5. Expanded Mode .............................................................................................. 11-15
Figure 11-6. Implementation of Expanded Mode Sources................................................... 11-16
Figure 11-7. Interrupt Sampling ........................................................................................... 11-20
Figure 11-8. Interrupt Control (ICON) Register.................................................................... 11-22
Figure 11-9. Interrupt Mapping (IMAP0-IMAP2) Registers .................................................. 11-24
Figure 11-10. Interrupt Pending (IPND) Register................................................................... 11-25
Figure 11-11. Interrupt Mask (IMSK) Registers ..................................................................... 11-26
Figure 11-12. Interrupt Controller........................................................................................... 11-30
Figure 11-13. Interrupt Service Flowchart.............................................................................. 11-34
Figure 12-1. Processor Initialization Flow .............................................................................. 12-2
Figure 12-2. Cold Reset Waveform ....................................................................................... 12-4
Figure 12-3. FAIL Sequence .................................................................................................. 12-8
Figure 12-4. Initial Memory Image (IMI) and Process Control Block (PRCB) ...................... 12-12
Figure 12-5. PMCON14_15 Register Bit Description in IBR ................................................ 12-15
Figure 12-6. Process Control Block Configuration Words.................................................... 12-17
Figure 12-7. Control Table ................................................................................................... 12-21
Figure 12-8. IEEE 1149.1 Device Identification Register..................................................... 12-22
Figure 12-9. V Current-Limiting Resistor........................................................................ 12-35
CC5
Figure 12-10. Reducing Characteristic Impedance................................................................ 12-36
Figure 12-11. Series Termination ......................................................................................... 12-39
Figure 12-12. AC Termination................................................................................................ 12-39
Figure 12-13. Avoid Closed-Loop Signal Paths ..................................................................... 12-41
Figure 13-1. PMCON and LMCON Example ......................................................................... 13-2
Figure 13-2. PMCON Register Bit Description....................................................................... 13-5
Figure 13-3. Bus Control Register (BCON)............................................................................ 13-6
Figure 13-4. Logical Memory Template Starting Address Registers (LMADR0-1) ................ 13-8
Figure 13-5. Logical Memory Template Mask Registers (LMMR0-1) .................................... 13-9
Figure 13-6. Default Logical Memory Configuration Register (DLMCON) ........................... 13-10
Figure 14.1. Bus States with Arbitration ................................................................................ 14-3
Figure 14-2. Data Width and Byte Encodings........................................................................ 14-7
Figure 14-3. Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus...... 14-10
Figure 14-4. 32-Bit Wide Data Bus Bursts ........................................................................... 14-12
Figure 14-5. 16-Bit Wide Data Bus Bursts ........................................................................... 14-12
Figure 14-6. 8-Bit Wide Data Bus Bursts ............................................................................. 14-13
Figure 14-7. Unaligned Write Transaction ........................................................................... 14-14
Figure 14-8. Burst Read and Write Transactions w/o Wait States, 32-bit Bus..................... 14-15
Figure 14-9. Burst Read and Write Transactions w/o Wait States, 8-bit Bus....................... 14-16
Figure 14-10. Burst Write Transactions With 2,1,1,1 Wait States, 32-bit Bus........................ 14-18
Figure 14-11. Burst Read/Write Transactions with 1,0 Wait States - Extra Tr State
on Read, 16-Bit Bus ........................................................................................ 14-20
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