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11.7.5
Interrupt Mapping Registers (IMAP0-IMAP2) ...................................................... 11-23
11.7.5.1
Interrupt Mask (IMSK) and Interrupt Pending (IPND) Registers ................... 11-25
11.7.5.2
Interrupt Controller Register Access Requirements ..................................... 11-27
11.7.5.3
Default and Reset Register Values .............................................................. 11-28
11.8
INTERRUPT OPERATION SEQUENCE................................................................... 11-28
11.8.1
Setting Up the Interrupt Controller ....................................................................... 11-31
11.8.2
Interrupt Service Routines ................................................................................... 11-31
11.8.3
Interrupt Context Switch ...................................................................................... 11-32
11.8.3.1
Servicing an Interrupt from Executing State ................................................. 11-32
11.8.3.2
Servicing an Interrupt from Interrupted State ............................................... 11-33
11.9
OPTIMIZING INTERRUPT PERFORMANCE ........................................................... 11-33
11.9.1
Interrupt Service Latency ..................................................................................... 11-35
11.9.2
Features to Improve Interrupt Performance ......................................................... 11-35
11.9.2.1
Vector Caching Option ................................................................................. 11-35
11.9.2.2
Caching Interrupt Routines and Reserving Register Frames ....................... 11-36
11.9.2.3
Caching the Interrupt Stack .......................................................................... 11-36
11.9.3
Base Interrupt Latency ........................................................................................ 11-37
11.9.4
Maximum Interrupt Latency ................................................................................. 11-38
11.9.4.1
Avoiding Certain Destinations for MDU Operations ..................................... 11-42
11.9.4.2
Masking Integer Overflow Faults for syncf ................................................... 11-42
CHAPTER 12
INITIALIZATION AND SYSTEM REQUIREMENTS
12.1
OVERVIEW ................................................................................................................. 12-1
12.2
INITIALIZATION .......................................................................................................... 12-2
12.2.1
Reset State Operation ........................................................................................... 12-3
12.2.2
Self Test Function (STEST, FAIL) ......................................................................... 12-6
12.2.2.1
The STEST Pin .............................................................................................. 12-7
12.2.2.2
External Bus Confidence Test ........................................................................ 12-7
12.2.2.3
The Fail Pin (FAIL) ......................................................................................... 12-7
12.2.2.4
IMI Alignment Check and System Error ......................................................... 12-8
12.2.2.5
FAIL Code ...................................................................................................... 12-8
12.3
Architecturally Reserved Memory Space .................................................................... 12-9
12.3.1
Initial Memory Image (IMI) ................................................................................... 12-10
12.3.1.1
Initialization Boot Record (IBR) .................................................................... 12-13
12.3.1.2
Process Control Block (PRCB) ..................................................................... 12-16
12.3.2
Process PRCB Flow ............................................................................................ 12-18
12.3.2.1
AC Initial Image ............................................................................................ 12-19
12.3.2.2
Fault Configuration Word ............................................................................. 12-19
12.3.2.3
Instruction Cache Configuration Word ......................................................... 12-19
12.3.2.4
Register Cache Configuration Word ............................................................. 12-19
12.3.3
Control Table ....................................................................................................... 12-20
12.4
DEVICE IDENTIFICATION ON RESET .................................................................... 12-22
12.4.1
Reinitializing and Relocating Data Structures ...................................................... 12-22
12.5
Startup Code Example .............................................................................................. 12-23
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