Supervisor Trace; Mark Trace; Software Breakpoints; Hardware Breakpoints - Intel i960 Jx Developer's Manual

Microprocessor
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If another trace event occurs at the same time as the prereturn-trace event, the processor generates a
fault on the non-prereturn-trace event first. Then, on a return from that fault handler, it generates a
fault on the prereturn-trace event. The prereturn trace is the only trace event that can cause two
successive trace faults to be generated between instruction boundaries.
9.2.6

Supervisor Trace

When supervisor-trace mode is enabled in TC and PC.te is set, the processor generates a super-
visor-trace fault after either of the following:
A call-system instruction (
a system-supervisor call.
A
instruction executes from supervisor mode and the return-type field is set to 010
ret
(i.e., return from
calls
).
This trace mode allows a debugging program to determine kernel-procedure call boundaries within
the instruction stream.
9.2.7

Mark Trace

Mark trace mode allows trace faults to be generated at places other than those specified with the
other trace modes, using the
in the fault record is used to indicate a match of the instruction-address breakpoint registers or the
data-address breakpoint registers as well as the
9.2.7.1

Software Breakpoints

and
allow breakpoint trace faults to be generated at specific points in the instruction
mark
fmark
stream. When mark trace mode is enabled and PC.te is set, the processor generates a mark trace
fault any time it encounters a
fault regardless of whether or not mark trace mode is enabled, provided PC.te is set. If PC.te is
clear,
and
behave like no-ops.
mark
fmark
9.2.7.2

Hardware Breakpoints

The hardware breakpoint registers are provided to enable generation of trace faults on instruction
execution and data access.
The i960 Jx processor implements two instruction and two data address breakpoint registers,
denoted IPB0, IPB1, DAB0 and DAB1. The instruction and data address breakpoint registers are
32-bit registers. The instruction breakpoint registers cause a break after execution of the target
instruction. The DABx registers cause a break after the memory access has been issued to the bus
controller, or the data cache.
) executes from user mode and the procedure table entry is for
calls
instruction. It should be noted that the MARK fault subtype bit
mark
fmark
and
mark
instruction.
fmark
causes the processor to generate a mark trace
TRACING AND DEBUGGING
mark
instructions.
or 011
2
2
9
9-5

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