Programming The Physical Memory Attributes (Pmcon Registers); Table 13-1. Pmcon Address Mapping - Intel i960 Jx Developer's Manual

MEMORY CONFIGURATION
13.3

Programming the Physical Memory Attributes (PMCON Registers)

The layout of the Physical Memory Configuration registers, PMCON0_1 through PMCON14_15,
is shown in Figure 13-2, which gives the descriptions of the individual bits. The PMCON registers
reside within memory-mapped control register space. Each PMCON register controls one
512-Mbyte region of memory according to the mapping shown in
Register (Control Table Entry)
PMCON0_1
PMCON2_3
PMCON4_5
PMCON6_7
PMCON8_9
PMCON10_11
PMCON12_13
PMCON14_15
13-4

Table 13-1. PMCON Address Mapping

0000.0000H to 0FFF.FFFFH
1000.0000H to 1FFF.FFFFH
2000.0000H to 2FFF.FFFFH
3000.0000H to 3FFF.FFFFH
4000.0000H to 4FFF.FFFFH
5000.0000H to 5FFF.FFFFH
6000.0000H to 6FFF.FFFFH
7000.0000H to 7FFF.FFFFH
8000.0000H to 8FFF.FFFFH
9000.0000H to 9FFF.FFFFH
A000.0000H to AFFF.FFFFH
B000.0000H to BFFF.FFFFH
C000.0000H to CFFF.FFFFH
D000.0000H to DFFF.FFFFH
E000.0000H to EFFF.FFFFH
F000.0000H to FFFF.FFFFH
Table 13-1
Region Controlled
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