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INSTRUCTION SET REFERENCE
6.2.27
eshro
Mnemonic:
eshro
Format:
eshro
Description:
Shifts src2 right by (src1
shifted beyond the least-significant bit are discarded.
src2 value is a long ordinal (i.e., 64 bits) contained in two adjacent registers.
src2 operand specifies the lower numbered register, which contains operand's
least significant bits. src2 operand must be an even numbered register (i.e.,
r4, r6, r8, ... or g0, g2).
src1 operand is a single 32-bit register or literal where the lower 5 bits
specify the number of places that the src2 operand is to be shifted.
The least significant 32 bits of the shift operation result are stored in dst.
Action:
if(reg_number(src2)%2 != 0)
{
dst[0] = undefined_value;
dst[1] = undefined_value;
generate_fault(OPERATION.INVALID_OPERAND);
}
else
dst = shift_right((src2 + reg_value(src2[1]) * 2**32),(src1%32))[31:0];
Faults:
STANDARD
Example:
eshro g3, g4, g11
Opcode:
eshro
See Also:
SHIFT, extract
Notes:
This core instruction is not implemented on the Kx and Sx 80960 processors.
6-50
Extended Shift Right Ordinal
src1,
src2,
reg/lit
reg/lit
mod
32) places and stores the result in dst. Bits
Refer to
# g11
g4,g5 shifted right by
# (g3 MOD 32).
5D8H
REG
dst
reg
section 6.1.6, "Faults" (pg.
6-5).
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