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12.2.2.1
The STEST Pin
The STEST pin enables and disables Built-In Self Test (BIST). BIST can be disabled if the initial-
ization time needs to be minimized or if diagnostics are simply not necessary. The STEST pin is
sampled on the rising edge of the RESET input:
•
If STEST is asserted (high), the processor executes the built-in self test.
•
If STEST is deasserted, the processor bypasses built-in self test.
12.2.2.2
External Bus Confidence Test
The external bus confidence test is always performed regardless of STEST pin value.
The external bus confidence test checks external bus functionality; it reads eight words from the
Initialization Boot Record (IBR) and performs a checksum on the words and the constant FFFF
FFFFH. The test passes only when the processor calculates a sum of zero (0). The external bus
confidence test can detect catastrophic bus failures such as external address, data or control lines
that are stuck, shorted or open.
12.2.2.3
The Fail Pin (FAIL)
The FAIL pin signals errors in either the built-in self test or bus confidence self test. FAIL is
asserted (low) for each self test
•
When any test fails, the FAIL pin remains asserted, a fail code message is driven onto the
address bus, and the processor stops execution at the point of failure.
•
When a system error occurs, FAIL is also asserted. See
Check and System Error" (pg. 12-8)
•
When the test passes, FAIL is deasserted.
If FAIL stays asserted, the only way to resume normal operation is to perform a reset operation.
When the STEST pin is used to disable the built-in self test, the test does not execute; however,
FAIL still asserts at the point where the built-in self test would occur. FAIL is deasserted after the
bus confidence test passes. In
Refer to
section 1.4, "Related Documents" (pg.
these documents.
INITIALIZATION AND SYSTEM REQUIREMENTS
(Figure
12-3):
for details.
Figure
12-3, all transitions on the FAIL pin are relative to CLKIN.
1-10). Further timing information can be found in
section 12.2.2.4, "IMI Alignment
12
12-7
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