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Manuals and User Guides for Intel 852GME. We have
1
Intel 852GME manual available for free PDF download: Design Manual
Intel 852GME Design Manual (323 pages)
Chipset Platforms
Brand:
Intel
| Category:
Computer Hardware
| Size: 3.58 MB
Table of Contents
Table of Contents
3
Introduction
19
Referenced Documents
20
Conventions and Terminology
21
System Overview
23
Intel 852GME Chipset Platform System Features
23
Host Interface
23
Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology on 90-Nm Process Technology
23
Mobile Intel Pentium 4 Processor
24
Intel Celeron D Processor on 90 Nm Process and in the 478-Pin Package
25
Intel Celeron Processor
25
Intel 852GME Graphics Memory Controller Hub (GMCH)
25
Multiplexed AGP and Intel DVO Interface
25
Accelerated Graphics Port (AGP) Interface
26
Integrated System Memory DRAM Controller
26
Internal Graphics Controller
26
Package/Power
27
Intel 82801DBM I/O Controller Hub 4-Mobile (ICH4-M)
27
Firmware Hub (FWH)
28
Figure 1. Intel 852GME GMCH System Block Diagram
29
Intel 852PM Chipset Platform System Features
30
Host Interface
30
Mobile Intel Pentium 4 Processor
30
Intel Celeron Processor
30
852PM Memory Controller Hub (MCH)
30
Accelerated Graphics Port (AGP) Interface
30
Integrated System Memory DRAM Controller
31
Package/Power
31
Intel 82801DBM I/O Controller Hub 4-Mobile (ICH4-M)
31
Firmware Hub (FWH)
31
Figure 2. Intel 852PM Chipset System Block Diagram
32
Intel 852GMV Chipset Platform System Features
33
Host Interface
33
Intel Celeron Processor
33
Intel 852GMV Graphics Memory Controller Hub (GMCH)
33
Multiplexed AGP and Intel DVO Interface
33
Integrated System Memory DRAM Controller
34
Internal Graphics Controller
34
Package/Power
34
Intel 82801DBM I/O Controller Hub 4-Mobile (ICH4-M)
35
Firmware Hub (FWH)
35
Figure 3. Intel 852GMV GMCH System Block Diagram
36
General Design Considerations
37
Recommended Board Stack-Up
37
Figure 4. Recommended Board Stack-Up Dimensions
38
Alternate Stack Ups
39
FSB Design Guidelines
41
FSB Routing Guidelines
41
Table 1. System Bus Routing Summary for the Processor
41
Figure 5. Cross-Sectional View of 2:1 Ratio
42
Return Path Evaluation
43
OPTIMIZED/COMPAT# Topology for Intel 852GME/852GMV/852PM Only Platforms
43
Figure 6. Cross-Sectional View of 2.5:1 Ratio
43
General Topology and Layout Guidelines
44
Data Signals
44
Address Signals
44
Strobe Signals
44
Common Clock Signals
44
Source Synchronous (SS) Signals
45
Figure 7. Processor Topology
45
Table 2. Processor System Bus Data Signal Routing Guidelines
45
Table 3. Processor System Bus Address Signal Routing Guidelines
45
Common Clock (CC) AGTL+ Signals
46
Figure 8. SS Topology for Address and Data
46
Table 4. Processor System Bus Control Signal Routing Guidelines
46
Asynchronous AGTL+ Signals
47
Topologies
47
Topology 1A: Open Drain (OD) Signals Driven by the Processor - IERR# and FERR
47
Figure 9. Routing Illustration for Topology 1A
47
Table 5. Layout Recommendations for Topology 1A
47
Topology 1B: Open Drain (OD) Signals Driven by the Processor -THERMTRIP
48
Figure 10. Routing Illustration for Topology 1B
48
Table 6. Layout Recommendations for Topology 1B
48
Topology 1C: Open Drain (OD) Signals Driven by the Processor -PROCHOT
49
Figure 11. Routing Illustration for Topology 1C
49
Table 7. Layout Recommendations for Topology 1C
49
Topology 2A: Open Drain (OD) Signals Driven by ICH4-M - PWRGOOD
50
Figure 12. Routing Illustration for Topology 2A
50
Table 8. Layout Recommendations for Topology 2A
50
Topology 2B: CMOS Signals Driven by ICH4-M - DPSLP
51
Figure 13. Routing Illustration for Topology 2B
51
Table 9. Layout Recommendations for Topology 2B
51
Topology 2C: CMOS Signals Driven by ICH4-M - A20M#, IGNNE#, LINT0/INTR, LINT1/NMI, SLP#, SMI#, and STPCLK
52
Figure 14. Routing Illustration for Topology 2C
52
Table 10. Layout Recommendations for Topology 2C
52
Topology 3: CMOS Signals Driven by ICH4-M to CPU and FWH - INIT
53
Figure 15. Routing Illustration for Topology 3
53
Table 11. Layout Recommendations for Topology 3
53
Voltage Translation Circuit
54
AGTL+ I/O Buffer Compensation
54
Figure 16. Voltage Translation Circuit for 3.3-V Receivers
54
Mobile Intel Pentium 4 Processor AGTL+ I/O Buffer Compensation
55
Processor RESET# Signal
55
Figure 17. Routing Recommendation for COMP[1:0]
55
Table 12. Layout Recommendation for COMP[1:0]
55
Figure 18. Processor RESET# Signal Routing Topology with no ITP700FLEX Connector
56
Figure 19. Processor RESET# Signal Routing Topology with ITP700FLEX Connector
56
Host Vrefs
57
ITP Debug Port
57
Logic Analyzer Interface (LAI)
57
Mechanical Considerations
57
Electrical Considerations
57
Table 13. Processor RESET# Signal Routing Guidelines with ITP700FLEX Connector
57
Mobile Intel Pentium 4 Processor and 852Gme/852Gmv/852Pmchipset FSB Signal Package Lengths
58
Table 14. Mobile Intel Pentium 4 Processor and 852GME Chipset Package Lengths
58
Platform Power Requirements
63
System Memory Design Guidelines (DDR-SDRAM)
65
Table 15. GMCH/MCH Chipset Memory Signal Groups
65
Length Matching and Length Formulas
66
Package Length Compensation
66
Table 16. Intel 852Gme/852Gmv/852Pmchipset GMCH/MCH DDR 333 Length Matching
66
Topologies and Routing Guidelines
67
Clock Signals - SCK[5:0], SCK#[5:0]
67
Clock Topology Diagram
67
Figure 20. Memory Clock Routing Topology SCK/SCK#[5:0]
67
Table 17. Clock Signal Mapping
67
Memory Clock Routing Guidelines
68
Table 18. Clock Signal Group Routing Guidelines
68
Clock Length Matching Requirements
69
Clock Reference Lengths
70
Figure 21. Memory Clock Trace Length Matching Diagram
70
Clock Package Length Table
71
Table 19. Memory Clock Package Lengths
71
Clock Routing Example
72
Data Signals - SDQ[71:0], SDM[8:0], SDQS[8:0]
72
Figure 22. Clock Signal Routing Example
72
Data Bus Topology
74
Figure 23. Data Signal Routing Topology
74
Table 20. Intel 852GME Chipset GMCH/MCH Memory Data Signal Group Routing
74
SDQS to Clock Length Matching Requirements
75
Figure 24. SDQS to Clock Trace Length Matching Diagram
76
Data to Strobe Length Matching Requirements
77
SDQ to SDQS Mapping
77
Table 21. SDQ/SDM to SDQS Mapping
77
Figure 25. SDQ/SDM to SDQS Trace Length Matching Diagram
78
SDQ/SDQS Signal Package Lengths
79
Table 22. Memory SDQ/SDM/SDQS Package Lengths
79
Memory Data Routing Example
80
Figure 26. Data Signals Group Routing Example
80
Control Signals - SCKE[3:0], SCS#[3:0]
81
Table 23. Control Signal to SO-DIMM Mapping
81
Control Signal Topology
82
Control Signal Routing Guidelines
82
Figure 27. Control Signal Routing Topology
82
Table 24. Control Signal Routing Guidelines
82
Control to Clock Length Matching Requirements
83
Figure 28. Control Signal to Clock Trace Length Matching Diagram
84
Memory Control Routing Example
85
Figure 29. Control Signals Group Routing Example
85
Control Group Package Length Table
86
Command Signals - SMA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE
86
Table 25. Control Group Package Lengths
86
Command Topology 1
87
Figure 30. Command Routing for Topology 1
87
Command Topology 1 Routing Guidelines
88
Table 26. Command Topology 1 Routing Guidelines
88
Command Topology 1 Length Matching Requirements
89
Figure 31. Topology 1 Command Signal to Clock Trace Length Matching Diagram
90
Command Topology 2
91
Figure 32. Command Routing Topology 2
91
Command Topology 2 Routing Guidelines
92
Table 27. Command Topology 2 Routing Guidelines
92
Command Topology 2 Length Matching Requirements
93
Figure 33. Topology 2 Command Signal to Clock Trace Length Matching Diagram
94
Command Topology 2 Routing Example
95
Figure 34. Example of Command Signal Group
95
Command Topology 3
96
Figure 35. Command Routing Topology 3
96
Command Topology 3 Routing Guidelines
97
Table 28. Command Topology 3 Routing Guidelines
97
6.3.4.10. Command Topology 3 Length Matching Requirements
98
Figure 36. Topology 3 Command Signal to Clock Trace Length Matching Diagram
99
6.3.4.11. Command Group Package Length Table
100
Table 29. Command Group Package Lengths
100
CPC Signals - SMA[5,4,2,1], SMAB[5,4,2,1]
101
Table 30. CPC Signal to SO-DIMM Mapping
101
CPC Signal Topology
102
CPC Signal Routing Guidelines
102
Figure 37. Command Per Clock Signal Routing Topology
102
Table 31. CPC Signal Routing Guidelines
102
CPC to Clock Length Matching Requirements
103
CPC Group Package Length Table
104
Figure 38. CPC Signals to Clock Length Matching Diagram
104
Table 32. CPC Group Package Lengths
104
Feedback - RCVENOUT#, RCVENIN
105
Routing Updates for "High-Density" Memory Device Support
105
ECC Disable Guidelines
105
GMCH/MCH ECC Functionality Disable
105
DDR Memory ECC Functionality Disable
106
System Memory Compensation
106
SMVREF Generation
106
DDR Power Delivery
106
External Thermal Sensor Based Throttling (ETS#)
107
ETS# Usage Model
107
ETS# Design Guidelines
107
Thermal Sensor Routing and Placement Guidelines
107
Figure 39. DDR Memory Thermal Sensor Placement
108
Integrated Graphics Display Port
109
Analog RGB/CRT Guidelines
109
Ramdac/Display Interface
109
Reference Resistor (REFSET)
109
RAMDAC Board Design Guidelines
110
Figure 40. Rset Placement
110
RAMDAC Routing Guidelines
111
Figure 41. GMCH DAC Routing Guidelines with Docking Connector
111
Table 33. Recommended GMCH DAC Components
112
DAC Power Requirements
113
Figure 42. DAC R, G, B Routing and Resistor Layout Example
113
HSYNC and VSYNC Design Considerations
114
DDC and I2C Design Considerations
114
LVDS Transmitter Interface
114
LVDS Length Matching Constraints
115
LVDS Package Length Compensation
115
Table 34. Signal Group and Signal Pair Names
115
LVDS Routing Guidelines
116
Table 35. LVDS Signal Group Routing Guidelines
116
Table 36. LVDS Package Lengths
117
Digital Video out Port
118
DVO Interface Signal Groups
118
DVOB Interface Signals
118
DVOC Interface Signals
118
Common Signals for both DVO Ports
119
DVOB and DVOC Port Interface Routing Guidelines
119
Length Mismatch Requirements
119
Table 37. DVO Interface Trace Length Mismatch Requirements
119
Package Length Compensation
120
DVOB and DVOC Routing Guidelines
120
Table 38. DVOB and DVOC Routing Guideline Summary
120
Table 39. DVOB Interface Package Lengths
121
DVOB and DVOC Port Termination
122
DVOB and DVOC Assumptions, Definitions, and Specifications
122
Table 40. DVOC Interface Package Lengths
122
DVOB and DVOC Simulation Method
123
Figure 43. DVOB and DVOC Simulations Model
123
Figure 44. Driver-Receiver Waveforms Relationship Specification
123
DVOB and DVOC Port Flexible (Modular) Design
124
DVOB and DVOC Module Design
124
Figure 45. DVO Enabled Simulation Model
124
Table 41. Allowable Interconnect Skew Calculation
124
Generic Connector Model
125
DVO GMBUS and DDC Interface Considerations
125
Figure 46. Generic Module Connector Parasitic Model
125
Table 42. DVO Enabled Routing Guideline Summary
125
Leaving the GMCH DVOB or DVOC Port Unconnected
126
Table 43. GMBUS Pair Mapping and Options
126
Miscellaneous Input Signals and Voltage Reference
127
Figure 47. GVREF Reference Voltage
127
AGP Port Design Guidelines
128
AGP Interface
128
Agp 2.0
128
AGP Interface Signal Groups
129
Table 44. AGP 2.0 Signal Groups
129
AGP Routing Guidelines
130
Timing Domain Routing Guidelines
130
Trace Length Requirements for AGP 1X
130
Table 45. AGP 2.0 Data/Strobe Associations
130
Trace Spacing Requirements
131
Trace Length Mismatch
131
2X/4X Timing Domain Routing Guidelines
131
Trace Length Requirements for AGP 2X/4X
131
Table 46. Layout Routing Guidelines for AGP 1X Signals
131
Trace Spacing Requirements
132
Figure 48. AGP Layout Guidelines
132
Trace Length Mismatch Requirements
133
Table 47. Layout Routing Guidelines for AGP 2X/4X Signals
133
Table 48. AGP 2.0 Data Lengths Relative to Strobe Length
133
AGP Clock Skew
134
AGP Signal Noise Decoupling Guidelines
134
Table 49. AGP 2.0 Routing Guideline Summary
134
AGP Interface Package Lengths
135
Table 50. AGP Interface Package Lengths
135
AGP Routing Ground Reference
136
Pull-Ups
136
Table 51. AGP Pull-Up/Pull-Down Requirements and Straps
137
Table 52. AGP 2.0 Pull-Up Resistor Values
137
AGP VDDQ and VCC
138
VREF Generation for AGP 2.0 (2X and 4X)
138
V AGP Interface (2X/4X)
138
AGP Compensation
138
PM_SUS_CLK/AGP_PIPE# Design Consideration
138
Figure 49. DPMS Circuit
139
Hub Interface
140
Hub Interface Compensation
140
Figure 50. Hub Interface Routing Example
140
Table 53. Hub Interface RCOMP Resistor Values
140
Hub Interface Data HL[10:0] and Strobe Signals
141
HL[10:0] and Strobe Signals Internal Layer Routing
141
Table 54. Hub Interface Signals Internal Layer Routing Summary
141
Table 55. Hub Interface Package Lengths for ICH4-M
142
Table 56. Hub Interface Package Lengths for GMCH
142
Terminating HL[11]
143
Hub VREF/VSWING Generation/Distribution
143
Single Generation Voltage Reference Divider Circuit
143
Table 57. Hub Interface VREF/VSWING Reference Voltage Specifications
143
Locally Generated Voltage Reference Divider Circuit
144
Figure 51. Single VREF/VSWING Voltage Generation Circuit for Hub Interface
144
Table 58. Recommended Resistor Values for Single VREF/VSWING Divider Circuit
144
Single GMCH and ICH4-M Voltage Generation / Separate Divider Circuit for VSWING/VREF
145
Figure 52. ICH4-M and GMCH Locally Generated Reference Voltage Divider Circuit
145
Figure 53. Shared GMCH and ICH4-M Reference Voltage with Separate Voltage Divider Circuit for VSWING and VREF
145
Table 59. Recommended Resistor Values for Separate HIVREF and HI_VSWING
145
Separate GMCH and ICH4-M Voltage Generation / Separate Divider Circuits for VREF and VSWING
146
Hub Interface Decoupling Guidelines
146
Figure 54. Individual HIVREF and HI_VSWING Voltage Reference Divider Circuits for ICH4-M and GMCH
146
Table 60. Recommended Resistor Values for HIVREF and HI_VSWING Divider Circuits for ICH4-M
146
I/O Subsystem
148
IDE Interface
148
Cabling
148
Primary IDE Connector Requirements
149
Figure 55. Connection Requirements for Primary IDE Connector
149
Secondary IDE Connector Requirements
150
Figure 56. Connection Requirements for Secondary IDE Connector
150
Mobile IDE Swap Bay Support
151
10.1.4.1. ICH4-M IDE Interface Tri-State Feature
151
S5/G3 to S0 Boot up Procedures for IDE Swap Bay
152
10.1.4.3. Power down Procedures for Mobile Swap Bay
152
10.1.4.4. Power up Procedures after Device "Hot" Swap Completed
152
Pci
153
Ac'97
153
Figure 57. PCI Bus Layout Example
153
Figure 58. Intel 82801DBM ICH4-M AC'97 - Codec Connection
154
Figure 59. Intel 82801DBM ICH4-M AC'97 - AC_BIT_CLK Topology
155
Figure 60. Intel 82801DBM AC'97 - AC_SDOUT/AC_SYNC Topology
155
Table 61. AC'97 AC_BIT_CLK Routing Summary
155
Figure 61. Intel 82801DBM AC'97 - AC_SDIN Topology
156
Table 62. AC'97 AC_SDOUT/AC_SYNC Routing Summary
156
Table 63. AC'97 AC_SDIN Routing Summary
156
AC'97 Routing
157
Motherboard Implementation
157
10.3.2.1. Valid Codec Configurations
158
SPKR Pin Configuration
158
Table 64. Supported Codec Configurations
158
USB 2.0 Guidelines and Recommendations
159
Layout Guidelines
159
10.4.1.1. General Routing and Placement
159
Figure 62. Example Speaker Circuit
159
10.4.1.2. USB 2.0 Trace Separation
160
10.4.1.3. USBRBIAS Connection
160
Figure 63. Recommended USB Trace Spacing
160
10.4.1.4. USB 2.0 Termination
161
10.4.1.5. USB 2.0 Trace Length Pair Matching
161
10.4.1.6. USB 2.0 Trace Length Guidelines
161
Figure 64. USBRBIAS Connection
161
Table 65. USBRBIAS/USBRBIAS# Routing Summary
161
Table 66. USB 2.0 Trace Length Guidelines (with Common-Mode Choke)
161
Plane Splits, Voids, and Cut-Outs (Anti-Etch)
162
VCC Plane Splits, Voids, and Cut-Outs (Anti-Etch)
162
GND Plane Splits, Voids, and Cut-Outs (Anti-Etch)
162
USB Power Line Layout Topology
162
EMI Considerations
163
10.4.4.1. Common Mode Chokes
163
Figure 65. Good Downstream Power Connection
163
Figure 66. Common Mode Choke Schematic
163
Esd
164
USB Selective Suspend
164
I/O APIC (I/O Advanced Programmable Interrupt Controller)
164
Smbus 2.0/Smlink Interface
165
Smbus Architecture and Design Considerations
166
10.6.1.1. Smbus Design Considerations
166
Figure 67. SMBUS 2.0/Smlink Protocol
166
10.6.1.2. General Design Issues/Notes
167
10.6.1.3. High Power/Low Power Mixed Architecture
167
10.6.1.4. Calculating the Physical Segment Pull-Up Resistor
167
Figure 68. High Power/Low Power Mixed V
167
Table 67. Bus Capacitance Reference Chart
168
Table 68. Bus Capacitance/Pull-Up Resistor Relationship
168
Fwh
169
FWH Decoupling
169
In Circuit FWH Programming
169
FWH INIT# Voltage Compatibility
169
FWH VPP Design Guidelines
170
FWH INIT# Assertion/Deassertion Timings
170
Figure 69. FWH VPP Isolation Circuitry
170
Rtc
171
Figure 70. RTCX1 and SUSCLK Relationship in ICH4-M
171
Figure 71. External Circuitry for the ICH4-M Where the Internal RTC Is Not Used
171
RTC Crystal
172
Figure 72. External Circuitry for the ICH4-M RTC
172
Table 69. RTC Routing Summary
172
External Capacitors
173
RTC Layout Considerations
174
RTC External Battery Connections
174
RTC External RTCRST# Circuit
175
Figure 73. Diode Circuit to Connect RTC External Battery
175
Figure 74. RTCRST# External Circuit for the ICH4-M RTC
175
VBIAS DC Voltage and Noise Measurements
176
Susclk
176
RTC-Well Input Strap Requirements
176
Internal LAN Layout Guidelines
176
Footprint Compatibility
177
Figure 75. Intel 82801DBM ICH4-M/Platform LAN Connect Section
177
Table 70. LAN Component Connections/Features
177
Intel 82801DBM ICH4-M - LAN Connect Interface Guidelines
178
10.9.2.1. Bus Topologies
178
10.9.2.1.1. LOM (LAN on Motherboard) Point-To-Point Interconnect
178
Figure 76. Single Solution Interconnect
178
Table 71. LAN Design Guide Section Reference
178
10.9.2.2. Signal Routing and Layout
179
10.9.2.3. Crosstalk Consideration
179
10.9.2.4. Impedances
179
Figure 77. LAN_CLK Routing Example
179
Table 72. LAN LOM Routing Summary
179
10.9.2.5. Line Termination
180
10.9.2.6. Terminating Unused LAN Connect Interface Signals
180
Intel 82562ET / Intel 82562EM Guidelines
180
Guidelines for Intel 82562ET / Intel 82562EM Component Placement
180
10.9.3.2. Crystals and Oscillators
180
10.9.3.3. Intel 82562ET / Intel 82562EM Termination Resistors
181
10.9.3.4. Critical Dimensions
181
Figure 78. Intel 82562ET / Intel 82562EM Termination
181
Figure 79. Critical Dimensions for Component Placement
181
Distance from Magnetics Module to RJ-45 (Distance A)
182
Distance from Intel 82562ET / 82562ET to Magnetics Module (Distance B)
182
10.9.3.5. Reducing Circuit Inductance
182
10.9.3.5.1. Terminating Unused Connections
183
10.9.3.5.2. Termination Plane Capacitance
183
Figure 80. Termination Plane
183
Intel 82562ET/EM Disable Guidelines
184
Design and Layout Consideration for Intel 82540EP / 82551QM
184
Figure 81. Intel 82562ET/EM Disable and Power down Circuitry
184
Table 73. Intel 82562ET/EM Control Signals
184
General Intel 82562ET/82562EM/82551QM/82540EP Differential Pair Trace Routing Considerations
185
10.9.6.1.1. Trace Geometry and Length
186
10.9.6.1.2. Signal Isolation
186
Figure 82. Trace Routing
186
10.9.6.1.3. Magnetics Module General Power and Ground Plane Considerations
187
Figure 83. Ground Plane Separation
187
Common Physical Layout Issues
188
Power Management Interface
189
10.10.1. SYS_RESET# Usage Model
189
10.10.2. PWRBTN# Usage Model
189
10.10.3. Power Well Isolation Control Strap Requirements
189
CPU CMOS Considerations
190
Figure 84. RTC Power Well Isolation Control
190
Figure 85. ICH4-M CPU CMOS Signals with CPU and FWH
191
Platform Clock Routing Guidelines
193
System Clock Groups
193
Table 74. Individual Clock Breakdown
193
Figure 86. Clock Distribution Diagram
194
Clock Group Topologies and Routing Constraints
195
Host Clock Group
195
Figure 87. Source Shunt Termination Topology
195
Table 75. Host Clock Group Routing Constraints
196
11.2.1.1. Host Clock Group General Routing Guidelines
197
11.2.1.2. Clock to Clock Length Matching and Compensation
197
11.2.1.3. EMI Constraints
197
CLK66 Clock Group
198
Figure 88. CLK66 Clock Group Topology
198
Table 76. CLK66 Clock Group Routing Constraints
198
Host Clock to CLK66 Routing Recommendations
199
Figure 89. BCLK to GCLKIN Timing Requirement
199
CLK33 Clock Group
200
Figure 90. CLK33 Group Topology
200
Table 77. CLK33 Clock Group Routing Constraints
200
PCI Clock Group
201
Figure 91. PCI Clock Group Topology
201
Table 78. PCICLK Clock Group Routing Constraints
201
CLK14 Clock Group
202
Figure 92. CLK14 Clock Group Topology
202
Table 79. CLK14 Clock Group Routing Constraints
202
DOTCLK Clock Group
203
Figure 93. DOTCLK Clock Topology
203
Table 80. DOTCLK Clock Routing Constraints
203
SSCCLK Clock Group
204
Figure 94. SSCCLK Clock Topology
204
Table 81. SSCCLK Clock Routing Constraints
204
USBCLK Clock Group
205
Clock Power Supply Decoupling
205
Figure 95. USBCLK Clock Topology
205
Table 82. USBCLK Clock Routing Constraints
205
PWRDWN# Signal Connections
206
Platform Power Delivery Guidelines
207
Definitions
207
Platform Power Requirements
208
Figure 96. Platform Power Delivery Architectural Block Diagram
208
Voltage Supply
209
Power Management States
209
Table 83. Power Management States
209
Power Supply Rail Descriptions
210
Table 84. Power Supply Rail Descriptions
210
852GME/852GMV/852PMGMCH/ICH4-M Platform Power-Up Sequence
211
Figure 97. GMCH / ICH4-M Platform Power-Up Sequence
211
Table 85. Timing Sequence Parameters for Figure 97
212
ICH4-M Power Sequencing Requirements
213
12.4.1.1. 3.3 V/1.5 V Power Sequencing
213
5REF / 3.3 V Sequencing
213
Figure 98. Power on Sequencing Timing Diagram (VR Circuitry)
213
Table 86. Timing Sequence Parameters for Figure 98
213
Design Guidelines
214
5Ref_Sus
214
Figure 99. Example V
214
Figure 100. V5REF_SUS with 5V_ALWAYS Connection Option (Recommended)
214
GMCH Power Sequencing Requirements
215
DDR Power Sequencing Requirements
215
Figure 101. V5REF_SUS with 3.3V_ALWAYS and VCC5 or VCC5_SUS Connection Option
215
PWR ICH4-M SYS_RESET# Signal
216
DDR Power Delivery Design Guidelines
216
Table 87. DDR Power-Up Initialization Sequence
216
DDR Interface Decoupling Guidelines
217
12.5.1.1. GMCH VCCSM Decoupling Guidelines
217
Figure 102. DDR Power Delivery Block Diagram
217
12.5.1.2. DDR SO-DIMM System Memory Decoupling Guidelines
218
V Power Delivery Guidelines
218
DDR Reference Voltage
218
Table 88. Absolute Vs. Relative Voltage Specification
219
Table 89. DDR-SDRAM SO-DIMM Voltage and Current Requirements
219
12.5.3.1. SMVREF Layout and Routing Recommendations
220
Table 90. Intel GMCH System Memory Voltage and Current Requirements
220
Table 91. Termination Voltage and Current Requirements
220
Table 92. GMCH System Memory I/O SMVREF Calculation
221
Table 93. Effects of Varying Resistor Values in the Divider Circuit
221
12.5.3.2. DDR VREF Requirements
222
DDR SMRCOMP Resistive Compensation
222
Table 94. DDR VREF Calculation
222
Table 95. Reference Distortion Due to Load Current
222
DDR VTT Termination
223
Figure 103. DDR SMRCOMP Resistive Compensation
223
Figure 104. SMVSWINGL and SMVSWINGH Reference Voltage Generation Circuit
223
Clock Driver Power Delivery Guidelines
224
Figure 105. Decoupling Capacitors Placement and Connectivity
225
Decoupling Recommendations
226
Processor Decoupling Guidelines
226
Intel 852GME/852GMV/852PMGMCH Decoupling Guidelines
226
Table 96. Processor Decoupling Recommendation
226
Table 97. GMCH Decoupling Recommendations
226
Intel ICH4-M Decoupling Guidelines
227
DDR VTT High Frequency and Bulk Decoupling
228
Figure 106. Minimized Loop Inductance Example
228
Table 98. Decoupling Requirements for the Intel ICH4-M
228
Hub Interface Decoupling
229
FWH Decoupling
229
General LAN Decoupling
229
Clock Driver Decoupling
229
Intel 852GME/852GMV/852PMGMCH Analog Power Delivery
230
Analog Supply Filter Requirements
230
Figure 107. Example Analog Supply Filter
230
Recommended Routing/Component Placement
231
Intel 852Gme/852Gmv/852Pmmaximum Supply Current Numbers
231
Table 99. Analog Supply Filter Requirements
231
Intel ICH4-M Power Consumption Numbers
232
Table 100. ICC Maximum Sustained Estimates (ICC REV0.3)
232
Table 101. Intel ICH4-M Power Consumption Measurements
232
Thermal Design Power
233
Table 102. Intel 852GME/852GMV/852PMGMCH Component Thermal Design Power
233
Table 103. Intel ICH4-M Component Thermal Design Power
233
Test Signals
234
Mobile Intel Pentium 4 Processor Reserved Signals
234
Intel 852GME / 852PM GMCH RSVD Signals
235
Table 104. GMCH "Intel Reserved" Signal Pin-Map Locations
235
Platform Design Checklist
236
General Information
236
Customer Implementation of Voltage Rails
237
Design Checklist Implementation
238
Figure 108. Routing Illustration for INIT
241
Figure 109. VCCIOPLL, VCCA and VSSA Power Distribution
241
Figure 110. Voltage Translation Circuit for PROCHOT
241
In Target Probe (ITP)
242
Decoupling Recommendations
242
Power-Up Sequence
243
Figure 111. Mobile Intel Pentium 4 Processor Power up Sequence
244
Clock Checklist
245
Resistor Recommendations
245
Figure 112. Clock Power-Down Implementation
246
852Gme/852Gmv/852Pmchecklist
247
System Memory
247
14.8.1.1. GMCH System Memory Interface
247
14.8.1.2. DDR SO-DIMM Interface
248
Figure 113. Reference Voltage Level for SMVREF
248
SO-DIMM Decoupling Recommendation
250
Fsb
250
Figure 114. 852GME HXSWING & HYSWING Reference Voltage Generation Circuit
250
Hub Interface
251
Graphics Interfaces
251
14.8.4.1. Lvds
251
14.8.4.2. Agp/Dvo
251
Figure 115. DPMS Clock Implementation
253
Figure 116. Q-SWITCH Circuit
254
Dac
255
Miscellaneous
256
Table 105. GST[2:0] Configurations
256
GMCH Decoupling Recommendations
257
GMCH Power-Up Sequence
258
Figure 117. 852GME Power-Up Sequence
258
ICH4-M Checklist
259
PCI Interface and Interrupts
259
Gpio
261
AGP_BUSY# Design Requirement
262
Smbus) System Management Interface
262
AC '97 Interface
263
ICH4-M Power Management Interface
264
FWH/LPC Interface
265
USB Interface
265
Hub Interface
265
Figure 118. Separated GMCH and ICH4-M VSWING/VREF Reference Voltage Circuit
266
Figure 119. Single or Locally Generated GMCH & ICH4-M HIVREF/HI_VSWING
267
Figure 120. Single Generated GMCH and ICH4-M VSWING/VREF Reference Voltage/ Local Voltage Divider Circuit for VSWING/VREF
267
14.9.10. RTC Circuitry
268
Figure 121. External Circuitry for the RTC
268
14.9.11. LAN Interface
269
14.9.12. Primary IDE Interface
269
14.9.13. Secondary IDE Interface
270
14.9.14. Miscellaneous Signals
270
14.9.15. ICH4-M Decoupling Recommendations
271
14.9.16. ICH4-M Power-Up Sequence
272
Table 106. ICH4-M Power-Up Timing Specifications
272
Figure 122. ICH4 Power-Up Sequence Waveforms
273
USB Power Checklist
274
14.10.1. Downstream Power Connection
274
Figure 123. Good Downstream Power Connection
274
FWH Checklist
275
14.12.1. Resistor Recommendations
275
Lan/Homepna Checklist
275
Resistor Recommendations (for 82562ET / 82562 EM)
275
14.12.2. Decoupling Recommendations
276
Figure 124. LAN_RST# Design Recommendation
276
Schematics
277
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