Intel i960 Jx Developer's Manual page 563

Microprocessor
Table of Contents

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A
absolute
displacement addressing mode
2-7
memory addressing mode
2-7
offset addressing mode
3-18
AC
AC register, see Arithmetic Controls (AC) register
3-7
access faults
access types
3-6
restrictions
ADD 6-7
add
6-7
conditional instructions
6-11
integer instruction
6-11
ordinal instruction
ordinal with carry instruction
6-10
addc
6-11
addi
6-7
addie
6-7
addig
6-7
addige
6-7
addil
6-7
addile
6-7
addine
6-7
addino
6-7
addio
6-11
addo
6-7
addoe
6-7
addog
6-7
addoge
6-7
addol
6-7
addole
6-7
addone
6-7
addono
6-7
addoo
address space restrictions
A-4
data structure alignment
A-2
instruction cache
A-2
internal data RAM
A-2
reserved memory
A-4
stack frame alignment
addressing mode
2-8
examples
register indirect
addressing registers and literals
alignment, registers and literals
2-7
alterbit
6-13
and
andnot
architecture reserved memory space
argument list
Arithmetic Controls (AC) Register
Arithmetic Controls (AC) register
condition code flags
initial image
initialization
integer overflow flag
integer overflow mask bit
no imprecise faults bit
6-10
arithmetic instructions
add, subtract, multiply or divide
extended-precision instructions
remainder and modulo instructions
shift and rotate instructions
arithmetic operations and data types
atadd
atmod
atomic access
atomic add instruction
atomic instructions
Atomic instructions (LOCK signal)
atomic modify instruction
atomic operations
atomic-read-modify-write sequence
B
6-16
b
6-17
bal
6-17
balx
basic bus states
6-19
bbc
6-19
bbs
BCON register, see Bus Control (BCON) register
BCU, see Bus Controller Unit
6-21
be
6-21
bg
bge
3-20
2-7
3-4
3-4
6-12
6-13
12-9
7-13
3-18
3-18
3-19
12-19
3-18
3-20
3-20
3-20
5-7
5-8
5-10
5-9
5-7
,
,
3-15
4-9
6-14
,
,
,
3-8
3-15
4-9
6-15
3-14
6-14
5-18
14-30
6-15
14-30
3-6
14-2
,
6-21
INDEX
5-8
Index-1

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