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Mode Field
Mode Description
000
Normal cache enabled
2
XX1
Full cache disabled
2
Load and lock one way
100
or 110
2
2
of the cache
31
Reserved - Set to zero
Figure 6-8. src/dst Interpretation for Breakpoint Resource Request
if (PC.em != supervisor)
Action:
generate_fault(TYPE.MISMATCH);
order_wrt(previous_operations);
OPtype = (src1 & 0xff00) >> 8;
switch (OPtype) {
case 0:
vector_to_post = 0xff & src1;
priority_to_post = vector_to_post >> 3;
pend_ints_addr = interrupt_table_base + 4 + priority_to_post;
pend_priority = memory_read(interrupt_table_base,atomic_lock);
# Priority zero just rescans Interrupt Table
if (priority_to_post != 0)
memory_write(interrupt_table_base,pend_priority,atomic_unlock);
# Update internal software priority with highest priority interrupt
# from newly adjusted Pending Priorities word. The current internal
# software priority is always replaced by the new, computed one. (If
# there is no bit set in pending_priorities word for the current
# internal one, then it is discarded by this action.)
if (pend_priority == 0)
else { msb_set = scan_bit(pend_priority);
# Make sure change to internal software priority takes full effect
Table 6-19. Cache Mode Configuration
80960JA
2 Kbyte
2 Kbyte
1 Kbyte
# Signal Software Interrupt
{pend_ints = memory_read(pend_ints_addr, non-cacheable)
pend_ints[7 & vector] = 1;
pend_priority[priority_to_post] = 1;
memory_write(pend_ints_addr, pend_ints); }
SW_Int_Priority = 0;
SW_Int_Priority = msb_set; }
INSTRUCTION SET REFERENCE
80960JF/JD
4 Kbyte
4 Kbyte
2 Kbyte
0
8
7
4
3
# available
# available
instruction
data
breakpoints
breakpoints
80960JT
16 Kbyte
16 Kbyte
8 Kbyte
6
6-115
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