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This chapter describes the i960
timer registers (TMRx, TCRx and TRRx), timer operation, timer interrupts, and timer register
values at initialization.
Each timer is programmed by the timer registers. These registers are memory-mapped within the
processor, addressable on 32-bit boundaries. When enabled, a timer decrements the user-defined
count value with each Timer Clock (TCLOCK) cycle. The countdown rate is also
user-configurable to be equal to the bus clock frequency, or the bus clock rate divided by 2, 4 or 8.
The timers can be programmed to either stop when the count value reaches zero (single-shot mode)
or run continuously (auto-reload mode). When a timer's count reaches zero, the timer's interrupt
unit signals the processor's interrupt controller.
functions. See also
Figure 10-5
Internal
CPU
Bus
Address
Detect
Fault
User/
Supervisor
Output
Status
®
Jx processor's dual, independent 32-bit timers. Topics include
Figure 10-1
for the Timer Unit state diagram.
Timer Mode Register
Timer Reload Register
32-bit Register
Timer Count Register
32-bit Counter
32-bit Compare
Against Zero
Terminal Count
Interrupt Unit
Interrupt
Output
Figure 10-1. Timer Functional Diagram
CHAPTER 10
TIMERS
shows a diagram of the timer
Clock Unit
Bus
Clock
Selected Clock
10
10-1
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