Table of Contents
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INDEX
6-112
subi
6-109
subie
6-109
subig
6-109
subige
6-109
subil
6-109
subile
6-109
subine
6-109
subino
6-109
subio
6-112
subo
6-109
suboe
6-109
subog
6-109
suboge
6-109
subol
6-109
subole
6-109
subone
6-109
subono
6-109
suboo
subtract
6-109
conditional instructions
6-112
integer instruction
6-112
ordinal instruction
ordinal with carry instruction
7-2
supervisor calls
3-23
supervisor mode resources
7-17
Supervisor Stack
,
3-1
3-12
supervisor stack
3-15
alignment
9-3
supervisor-trace mode
,
6-113
8-20
syncf
synchronize faults instruction
,
,
,
,
1-4
3-8
4-4
4-5
sysctl
3-23
A-3
,
7-2
7-15
system calls
7-2
calls
,
7-2
8-2
system-local
,
7-2
8-2
system-supervisor
6-114
system control instruction
,
3-1
3-12
system procedure table
3-15
alignment
T
,
3-23
9-2
TC
10-6
TCR0, TCR1
Index-14
Test Access Port (TAP) controller
architecture
Asynchronous Reset Input (TRST) pin
block diagram
Serial Test Data Output (TDO) pin
state diagram
Test Clock (TCK) pin
Test Mode Select (TMS) pin
test features
test instructions
Test Mode Select (TMS) line
teste
testg
testge
testl
testle
testne
testno
testo
32-bit bus width byte enable encodings
32-bit wide data bus bursts
timer
6-108
interrupts
memory-mapped addresses
Timer Count Register (TCR0, TCR1)
Timer Count Register (TCRx)
address and access type
Timer Mode Register
timer mode control bit summary
Timer Mode Register (TMR0, TMR1)
6-113
Timer Mode Register (TMRx)
,
,
,
,
4-6
6-114
9-6
address and access type
terminal count
timer clock encodings
Timer Reload Register (TRR0, TRR1)
Timer Reload Register (TRRx)
address and access type
timers
,
7-15
overview
TMR0, TMR1
Trace Controls (TC) Register
Trace Controls (TC) register
trace events
hardware breakpoint registers
15-2
15-3
15-3
15-4
15-5
15-5
15-2
6-118
15-2
6-118
6-118
6-118
6-118
6-118
6-118
6-118
6-118
14-12
11-9
10-2
10-6
3-11
10-8
3-11
10-4
10-6
3-11
1-6
10-3
,
3-23
,
3-23
9-1
9-1
15-5
15-5
14-8
10-6
10-3
10-7
9-2
9-2
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