Table 3-4. Supervisor Space Family Registers - Intel i960 Jx Developer's Manual

Table 3-4. Supervisor Space Family Registers

Register Name
Reserved
(DLMCON) Default Logical Memory Configuration
Register
Reserved
(LMADR0) Logical Memory Address Register 0
(LMMR0) Logical Memory Mask Register 0
(LMADR1) Logical Memory Address Register 1
(LMMR1) Logical Memory Mask Register 1
Reserved
(IPB0) Instruction Address Breakpoint Register 0
(IPB1) Instruction Address Breakpoint Register 1
Reserved
(DAB0) Data Address Breakpoint Register 0
(DAB1) Data Address Breakpoint Register 1
Reserved
(BPCON) Breakpoint Control Register
Reserved
(IPND) Interrupt Pending Register
(IMSK) Interrupt Mask Register
Reserved
(ICON) Interrupt Control Word
Reserved
(IMAP0) Interrupt Map Register 0
(IMAP1) Interrupt Map Register 1
(IMAP2) Interrupt Map Register 2
Reserved
PROGRAMMING ENVIRONMENT
(Sheet 1 of 2)
Memory-Mapped
Access Type
Address
FF00 8000H to
FF00 80FFH
FF00 8100H
FF00 8104H
FF00 8108H
FF00 810CH
FF00 8110H
FF00 8114H
FF00 8118H to
FF00 83FFH
FF00 8400H Sysctl- RwG/WwG
FF00 8404H Sysctl- RwG/WwG
FF00 8408H to
FF00 841FH
FF00 8420H R/W, WwG
FF00 8424H R/W, WwG
FF00 8428H to
FF00 843FH
FF00 8440H R/W, WwG
FF00 8444H to
FF00 84FFH
FF00 8500H
FF00 8504H
FF00 8508H to
FF00 850FH
FF00 8510H
FF00 8514H to
FF00 851FH
FF00 8520H
FF00 8524H
FF00 8528H
FF00 852CH to
FF00 85FFH
—
3
R/W
—
R/W
R/W
R/W
R/W
—
—
—
—
AtMod
AtMod
—
R/W
—
R/W
R/W
R/W
—
3-9