Data Address Breakpoint (Dab) Registers - Intel i960 Jx Developer's Manual

9.2.7.5

Data Address Breakpoint (DAB) Registers

The format for the Data Address Breakpoint (DAB) registers is shown in
breakpoint register contains a 32-bit address of a byte to match on.
A breakpoint is triggered when both a data access's type and address matches that specified by
BPCON and the appropriate DAB register. The mode bits for each DAB register, which are
contained in BPCON (see
access-type match selects that DAB register to perform address checking. An address match occurs
when the byte address of any of the bytes referenced by the data access matches the byte address
contained within a selected DAB.
Consider the following example. DAB0 is enabled to break on any data read access and has a value
of 100FH. Any of the following instructions will cause the DAB0 breakpoint to be triggered:
ldob 0x100f,r8
ldos 0x100e,r8
ld 0x100c,r8
ld 0x100d,r8
ldl 0x1008,r8
ldt 0x1004,r8
ldq 0x1000,r8
Note that the instruction:
ldt 0x1000,r8
does not cause the breakpoint to be triggered because byte 100FH is not referenced by the triple
word access.
Data address breakpoints can be set to break on any data read, any data write, or any data read or
data write access. All accesses qualify for checking. These include explicit load and store instruc-
tions, and implicit data accesses performed by other instructions and normal processor operations.
For data accesses to the memory-mapped control register space, it is unpredictable whether
breakpoint traces are generated when the access matches the breakpoints and also results in an
OPERATION fault or TYPE.MISMATCH fault. The OPERATION or TYPE.MISMATCH fault
will always be reported in this case.
section 9.2.7.4), qualify the access types that DAB will match. An
/* even unaligned accesses */
TRACING AND DEBUGGING
Figure 9-3. Each
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