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INTERRUPTS
The global interrupts enable bit (bit 10) globally enables or disables the external interrupt pins and
timer unit inputs. It does not affect the NMI pin. This bit performs the same function as clearing the
mask register. The global interrupts enable bit is also changed indirectly by the use of the following
instructions:
,
,
.
inten
intdis
intctl
The mask-operation field (bits 11, 12) determines the operation the core performs on the mask
register when a hardware-generated interrupt is serviced. On an interrupt, the IMSK register is
either unchanged; cleared for dedicated-mode interrupts; cleared for expanded-mode interrupts; or
cleared for both dedicated- and expanded-mode interrupts. IMSK is never cleared for NMI or
software interrupts.
The vector cache enable bit (bit 13) determines whether interrupt table vector entries are fetched
from the interrupt table or from internal data RAM. Only vectors with the four least-significant bits
equal to 0010
may be cached in internal data RAM.
2
The sampling-mode bit (bit 14) determines whether dedicated inputs and NMI pin are sampled
using debounce sampling or fast sampling. Expanded-mode inputs are always detected using
debounce mode.
Bits 15 through 31 are reserved and must be set to 0 at initialization.
11.7.5
Interrupt Mapping Registers (IMAP0-IMAP2)
The IMAP registers
(Figure
11-9) are three 32-bit registers (IMAP0 through IMAP2). These
registers are used to program the vector number associated with the interrupt source when the
source is connected to a dedicated-mode input. IMAP0 and IMAP1 contain mapping information
11
for the external interrupt pins (four bits per pin). IMAP2 contains mapping information for the
timer-interrupt inputs (four bits per interrupt).
Each set of four bits contains a vector number's four most-significant bits; the four least-significant
bits are always 0010
. In other words, each source can be programmed for a vector number of
2
PPPP 0010
, where "P" indicates a programmable bit. For example, IMAP0 bits 4 through 7
2
contain mapping information for the XINT1 pin. If these bits are set to 0110
, the pin is mapped to
2
vector number 0110 0010
(or vector number 98).
2
Software can access the mapping registers using load/store type instructions. The mapping
registers are also automatically loaded at initialization from the control table in external memory.
Note that bits 16 through 31 of IMAP0 and IMAP1 are reserved and should be set to 0 at initial-
ization. Bits 0-15 and 24-31 of IMAP2 are also reserved and should be set to 0.
11-23
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