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INITIALIZATION AND SYSTEM REQUIREMENTS
12.3.2
Process PRCB Flow
The following pseudo-code flow illustrates the processing of the PRCB. Note that this flow is used
for both initialization and reinitialization (through
Process_PRCB(prcb_ptr)
{
PRCB_mmr = prcb_ptr;
reset_state(data_ram); /* It is unpredictable whether the
/* Data RAM keeps its prior contents */
fault_table
=
memory[PRCB_mmr];
ctrl_table
=
memory[PRCB_mmr+0x4];
AC
=
memory[PRCB_mmr+0x8];
fault_config =
memory[PRCB_mmr+0xc];
if (1 & (fault_config >> 30)) generate_fault_on_unaligned_access = false;
else
/** Load Interrupt Table and Cache NMI Vector Entry in Data RAM**/
Reset_block_NMI;
interrupt_table =
memory[0] = memory[interrupt_table + (248*4) + 4];
/** Process System Procedure Table **/
sysproc = memory[PRCB_mmr+0x14];
temp
= memory[sysproc+0xc];
SSP_mmr = (~0x3) & temp;
SSP.te
= 1 & temp;
/** Initialize ISP, FP, SP, and PFP **/
ISP_mmr =
memory[PRCB_mmr+0x1c];
FP
= (~0xF) & ISP_mmr;
SP
= FP + 64;
PFP
= FP;
/** Initialize Instruction Cache **/
ICCW = memory[PRCB_mmr+0x20];
if (1 & (ICCW >> 16) ) disable(I_cache);
/** Configure Local Register Cache **/
programmed_limit = (7 & (memory[PRCB_mmr+0x24] >> 8) );
config_reg_cache( programmed_limit );
/** Load_control_table. **/
load_control_table(ctrl_table+0x10 , ctrl_table+0x58);
load_control_table(ctrl_table+0x68 , ctrl_table+0x6c);
IBP0 = 0x0; IBP1 = 0x0; DAB0 = 0x0; DAB1 = 0x0; BPCON = 0x0
/** Initialize Timers **/
TMR0.tc
= 0; TMR1.tc
TMR0.sup
= 0; TMR1.sup
TMR0.csel = 0; TMR1.csel = 0;
DLMCON.dcen = 0
LMMR0O.lmte = 0
LMMR1.lmte = 0
return;
}
12-18
sysctl
Example 12-2. Process PRCB Flow
generate_fault_on_unaligned_access = true;
memory[PRCB_mmr+0x10];
= 0; TMR0.enable = 0; TMR1.enable = 0;
= 0; TMR0.reload = 0; TMR1.reload = 0;
).
*/
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