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11.9.1
Interrupt Service Latency
The established measure of interrupt performance is the time required to perform an interrupt task
switch, which is known as interrupt service latency. Latency is the time measured between
activation of an interrupt source and execution of the first instruction for the accompanying
interrupt-handling procedure.
Interrupt latency depends on interrupt controller configuration and the instruction being executed
at the time of the interrupt. The processor also has a number of cache options that reduce interrupt
latency. In the discussion that follows, interrupt latency is expressed as a number of bus clock
cycles, and reflects differences between the 80960JA/JF, the 80960JD due to the 80960JD
processor's clock-doubled core, and the 80960JT due to the processor's clock-tripled core.
11.9.2
Features to Improve Interrupt Performance
The i960 Jx processor implementation employs four methods to reduce interrupt latency:
•
Caching interrupt vectors on-chip
•
Caching of interrupt handling procedure code
•
Reserving register frames in the local register cache
•
Caching the interrupt stack in the data cache
11.9.2.1
Vector Caching Option
To reduce interrupt latency, the i960 Jx processors allow some interrupt table vector entries to be
cached in internal data RAM. When the vector cache option is enabled and an interrupt request has
a cached vector to be serviced, the controller fetches the associated vector from internal RAM
rather than from the interrupt table in memory.
Interrupts with a vector number with the four least-significant bits equal to 0010
The vectors that can be cached coincide with the vector numbers that are selected with the mapping
registers and assigned to dedicated-mode inputs. The vector caching option is selected when
programming the ICON register; software must explicitly store the vector entries in internal RAM.
Since the internal RAM is mapped to the address space directly, this operation can be performed
using the core's store instructions.
locations in internal RAM. For example, the vector entry for vector number 18 must be stored at
RAM location 04H, and so on.
The NMI vector is also shown in
location 0000H. The processor automatically loads this location at initialization with the value of
vector number 248 in the interrupt table.
Table 11-2
shows the required vector mapping to specific
Table
11-2. This vector is always cached in internal data RAM at
INTERRUPTS
11
can be cached.
2
11-35
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