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At initialization, the control table automatically loads into the on-chip control registers. This action
simplifies the user's start-up code by providing a transparent setup of the processor's peripherals.
See
CHAPTER 12, INITIALIZATION AND SYSTEM
3.3.1.2
Access Faults
Memory-mapped registers are meant to be accessed only as aligned, word-size registers with
adherence to the appropriate access mode. Accessing these registers in any other way results in
faults or undefined operation. An access is performed using the following fault model:
1.
The access must be a word-sized, word-aligned access; otherwise, the processor generates an
OPERATION.UNIMPLEMENTED fault.
2.
When the access is a store in user mode to an implemented supervisor location, a
TYPE.MISMATCH fault occurs. It is unpredictable whether a store to an unimplemented
supervisor location causes a fault.
3.
When the access is neither of the above, the access is attempted. Note that an MMR may
generate faults based on conditions specific to that MMR. (Example: trying to write the
timer registers in user mode when they have been allocated to supervisor mode only.)
4.
When a store access to an MMR faults, the processor ensures that the store does not take effect.
5.
A load access of a reserved location returns an unpredictable value.
6.
Avoid any store accesses to reserved locations. Such a store can result in undefined operation
of the processor when the location is in supervisor space.
Instruction fetches from the memory-mapped register space are not allowed and result in an
OPERATION.UNIMPLEMENTED fault.
PROGRAMMING ENVIRONMENT
REQUIREMENTS.
3
3-7
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