Load - Intel i960 Jx Developer's Manual

INSTRUCTION SET REFERENCE
6.2.37

LOAD

Mnemonic: ld
ldob
ldos
ldib
ldis
ldl
ldt
ldq
Format: ld*
Description: Copies byte or byte string from memory into a register or group of successive
registers.
The src operand specifies the address of first byte to be loaded. The full range
of addressing modes may be used in specifying src. Refer to
DATA TYPES AND MEMORY ADDRESSING MODES
mation.
dst specifies a register or the first (lowest numbered) register of successive
registers.
and
ldob
a full 32-bit word. Data being loaded is sign-extended during integer loads
and zero-extended during ordinal loads.
ld , ldl ,
memory into successive registers.
For
ldl
and
ldq
g4, g8, g12, r4, r8, r12). Results are unpredictable when registers are not
aligned on the required boundary or when data extends beyond register g15
or r15 for
Action: ld:
dst = read_memory(effective_address)[31:0];
if((effective_address[1:0] != 00
generate_fault(OPERATION.UNALIGNED);
ldob:
dst[7:0] = read_memory(effective_address)[7:0];
dst[31:8] = 0x000000;
6-70
Load
Load Ordinal Byte
Load Ordinal Short
Load Integer Byte
Load Integer Short
Load Long
Load Triple
Load Quad
src, dst
mem reg
load a byte and
ldib ldos
ldt and ldq instructions copy 4, 8, 12 and 16 bytes, respectively, from
, dst must specify an even numbered register (i.e., g0, g2...). For
, dst must specify a register number that is a multiple of four (i.e., g0,
ldl , ldt or ldq .
) && unaligned _fault_enabled)
2
for more infor-
and load a half word and convert it to
ldis
CHAPTER 2,
ldt