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CLKIN
Outputs:
AD31:0,
ALE, ALE,
ADS, A3:2,
BE3:0,
WIDTH/HLTD1:0,
D/C, W/R,
DT/R, DEN,
BLAST, LOCK
HOLD
HOLDA
Figure 14-18. Arbitration Timing Diagram for a Bus Master
The HOLD/HOLDA arbitration functions during processor reset. The bus controller acknowledges
HOLD while RESET is asserted because the bus is idle. If RESET is asserted while HOLDA is asserted
(the processor has acknowledged the HOLD), the processor remains in the HOLDA state. The processor
does not continue reset activities until HOLD is removed and the processor removes HOLDA.
14.2.8.2
BSTAT Signal
The i960 Jx microprocessor extends the HOLD/HOLDA protocol with a bus status (BSTAT)
signal. In simplest terms, assertion of the BSTAT output pin indicates that the CPU may soon stall
unless it obtains (or retains) control of the bus. This indication is a useful input to arbitration logic,
whether or not the 80960 Jx is the primary bus master.
The processor asserts BSTAT when one or more of the following conditions are true:
•
The bus queue in the bus control unit (BCU) becomes full for any reason.
•
An instruction fetch request is pending or being serviced on the bus. This behavior promotes
performance by supporting instruction cache fills.
Ti or Tr
Th
Th
Valid
EXTERNAL BUS
Ti or Ta
Valid
F_XL013A
14
14-33
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