Intel i960 Jx Developer's Manual page 23

Table 14-7. Summary of Short Word Load and Store Accesses ........................................ 14-23
Table 14-8. Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4) ....................... 14-24
Table 14-9. Byte Ordering on Bus Transfers, Word Data Type .......................................... 14-28
Table 14-10. Byte Ordering on Bus Transfers, Short-Word Data Type ................................ 14-29
Table 14-11. Byte Ordering on Bus Transfers, Byte Data Type ........................................... 14-29
Table 15-1. TAP Controller Pin Definitions ........................................................................... 15-5
Table 15-2. Boundary Scan Instruction Set .......................................................................... 15-8
Table 15-3. Boundary Scan Register Bit Order .................................................................. 15-14
Table B-1. Miscellaneous Instruction Encoding Bits ............................................................. B-1
Table B-2. REG Format Instruction Encodings ..................................................................... B-2
Table B-3. COBR Format Instruction Encodings .................................................................. B-6
Table B-4. CTRL Format Instruction Encodings ................................................................... B-7
Table B-5. Cycle Counts for sysctl Operations ..................................................................... B-7
Table B-6. Cycle Counts for icctl Operations ........................................................................ B-8
Table B-7. Cycle Counts for dcctl Operations ....................................................................... B-8
Table B-8. Cycle Counts for intctl Operations ....................................................................... B-8
Table B-9. MEM Format Instruction Encodings .................................................................... B-9
Table B-10. Addressing Mode Performance ......................................................................... B-10
Table C-1. Instruction Field Descriptions .............................................................................. C-2
Table C-2. Encoding of src1 and src2 in REG Format .......................................................... C-3
Table C-3. Encoding of src/dst in REG Format ..................................................................... C-3
Table C-4. Encoding of src1 in COBR Format ...................................................................... C-3
Table C-5. Encoding of src2 in COBR Format ...................................................................... C-4
Table C-6. Addressing Modes for MEM Format Instructions................................................. C-5
Table C-7. Encoding of Scale Field ....................................................................................... C-6
Table D-1. Register and Data Structures .............................................................................. D-1
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