Table of Contents
Advertisement
case 6:
case 8:
default:
}
order_wrt(subsequent_operations)
;
STANDARD
Faults:
TYPE.MISMATCH
OPERATION.INVALID_OPERAND
# Store data cache sets to memory pointed to by src2.
start = src_dst[15:0]
end = src_dst[31:16]
if (end >= Dcache_max_sets) end = Dcache_max_sets - 1;
if (start > end) generate_fault
(OPERATION.INVALID_OPERAND);
memadr = src2;
if (0x3 & memadr! = 0)
generate_fault(OPERATION.INVALID_OPERAND)
for (set = start; set <= end; set++){
# Set_Data is described at end of this code flow.
memory[memadr] = Set_Data[set];
memadr += 4;
for (way = 0; way < numb_ways; way++)
{memory[memadr] = tags[set][way];
memadr += 4;
memory[memadr] = valid_bits[set][way];
memadr += 4;
for (word = 0; word < words_in_line; word++)
{memory[memadr] =
memadr += 4;
}
}
}
break;
# invalidate the lines that came from LMTs that had DCIIR set
# at the time the line was allocated.
# NOTE : for compatibility with future products that have
# several independent regions, the value of src2 should be one.
invalidate_DCIIR_lines_in_DCache;
break;
# Reserved.
generate_fault(OPERATION.INVALID_OPERAND);
break;
Refer to
Attempt to execute instruction while not in
supervisor mode.
INSTRUCTION SET REFERENCE
#
Starting set number.
#
Ending set number.
#
(zero-origin).
#
Must be word-aligned.
Dcache_line[set][way][word];
section 6.1.6, "Faults" (pg.
6
6-5).
6-45
Advertisement
Table of Contents
