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TEST ACCESS PORT (TAP)
controller state." In the implementation of RUNBIST used in the P6 family, the execution of
the BIST routine will not stop if the Run-Test/Idle state is exited before BIST is complete. In
all other regards, RUNBIST instruction operates exactly as defined in the 1149.1
specification.
Note that RUNBIST will not function when the processor core clock has been stopped. All
other 1149.1-defined instructions operate independently of the processor core clock.
The op-codes are 1149.1-compliant, and are consistent with the Intel-standard op-code
encodings and backward-compatible with the Pentium processor 1149.1 instruction op-codes.
6.4.
DATA REGISTER SUMMARY
Table 6-2 gives the complete list of test data registers which can be accessed through the
TAP. The MSB of the register is connected to TDI (for writing), and the LSB of the register
is connected to TDO (for reading) when that register is selected.
TAP Data Register
Bypass
Device ID
BIST Result
Boundary Scan
6.4.1.
Bypass Register
The Bypass register provides a short path between TDI and TDO. It is loaded with a logical 0
in the Capture-DR state.
6.4.2.
Device ID Register
The Device ID register contains the processor device identification code in the format shown
in Table 6-3. The manufacturer's identification code is unique to Intel. The part number code
is divided into four fields: V
processor), generation (sixth generation), and model. The version field is used for stepping
information.
6-8
Table 6-2. TAP Data Registers
Size
1
32
1
159
(2.8V supply), product type (an Intel Architecture compatible
CC
Selected by Instructions
BYPASS, HIGHZ, CLAMP
IDCODE
RUNBIST
EXTEST, SAMPLE/PRELOAD
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