Table B-3. Cobr Format Instruction Encodings - Intel i960 Jx Developer's Manual

OPCODES AND EXECUTION TIMES

Table B-3. COBR Format Instruction Encodings

20 testno
21 testg
22 teste
23 testge
24 testl
25 testne
26 testle
27 testo
30 bbc
31 cmpobg
32 cmpobe
33 cmpobge
34 cmpobl
35 cmpobne
36 cmpoble
37 bbs
38 cmpibno
39 cmpibg
3A cmpibe
3B cmpibge
3C cmpibl
3D cmpibne
3E cmpible
3F cmpibo
1. Indicates that it takes 2 cycles to execute the instruction plus an additional cycle to fetch the target
instruction if the branch is taken.
B-6
31 ........... 24 23 . 19 18... 14
dst
4 0010 0000
4 0010 0001 dst
dst
4 0010 0010
4 0010 0011 dst
4 0010 0100 dst
4 0010 0101 dst
dst
4 0010 0110
4 0010 0111 dst
1
bitpos
2 + 1 0011 0000
2 + 1 0011 0001 src1
2 + 1 0011 0010 src1
2 + 1 0011 0011 src1
src1
2 + 1 0011 0100
2 + 1 0011 0101 src1
src1
2 + 1 0011 0110
2 + 1 0011 0111 bitpos
2 + 1 0011 1000 src1
2 + 1 0011 1001 src1
src1
2 + 1 0011 1010
2 + 1 0011 1011 src1
src1
2 + 1 0011 1100
2 + 1 0011 1101 src1
2 + 1 0011 1110 src1
2 + 1 0011 1111 src1
13 12 ........ 2 1
M1 T
M1 T
M1 T
M1 T
M1 T
M1 T
M1 T
M1 T
src targ
M1 T
src2 M1 targ T
src2 M1 targ T
src2 M1 targ T
src2 targ
M1 T
src2 M1 targ T
src2 targ
M1 T
src M1 targ T
src2 M1 targ T
src2 M1 targ T
src2 targ
M1 T
src2 M1 targ T
src2 targ
M1 T
src2 M1 targ T
src2 M1 targ T
src2 M1 targ T
0
S2
S2
S2
S2
S2
S2
S2
S2
S2
S2
S2
S2
S2
S2
S2
S2
S2
S2
S2
S2
S2
S2
S2
S2