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11.4.1
Vector Entries
A vector entry contains a specific interrupt handler's address. When an interrupt is serviced, the
processor branches to the address specified by the vector entry.
Each interrupt is associated with an 8-bit vector number that points to a vector entry in the interrupt
table. The vector entry section contains 248 word-length entries. Vector numbers 8-243 and
252-255 and their associated vector entries are used for conventional interrupts. Vector numbers
244-247 and 249-251 are reserved. Vector number 248 and its associated vector entry is used for
the non-maskable interrupt (NMI). Vector numbers 0-7 cannot be used.
Vector entry 248 contains the NMI handler address. When the processor is initialized, the NMI vector
located in the interrupt table is automatically read and stored in location 0H of internal data RAM. The
NMI vector is subsequently fetched from internal data RAM to improve this interrupt's performance.
The vector entry structure is given at the bottom of
begin on a word boundary, so the processor assumes that the vector's two least significant bits
are 0. Bits 0 and 1 of an entry indicate entry type: on the i960 Jx processor, only type 00 is valid.
The other possible entry types are reserved and must not be used.
11.4.2
Pending Interrupts
The pending interrupts section comprises the interrupt table's first 36 bytes, divided into two fields:
pending priorities (byte offset 0 through 3) and pending interrupts (4 through 35).
Each of the 32 bits in the pending priorities field indicate an interrupt priority. When the processor
posts a pending interrupt in the interrupt table, the bit corresponding to the interrupt's priority is
set. For example, if an interrupt with a priority of 10 is posted in the interrupt table, bit 10 is set.
Each of the pending interrupts field's 256 bits represents an interrupt vector number. Byte offset 5
is for vectors 8 through 15, byte offset 6 is for vectors 16 through 23, and so on. Byte offset 4, the
first byte of the pending interrupts field, is reserved. When an interrupt is posted, its corresponding
bit in the pending interrupt field is set.
This encoding of the pending priority and pending interrupt fields permits the processor to first
check if there are any pending interrupts with a priority greater than the current program and then
determine the vector number of the interrupt with the highest priority.
Figure
11-2. Each interrupt procedure must
INTERRUPTS
11
11-5
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