Format Of A Virtual Address; Address Translation - Intel i86W Manual

ADDRESSING
Address translation is disabled when the processor is reset. It is enabled when a store to
dirbase
sets the ATE bit. It is disabled again when a store clears the ATE bit.
4.2.1 Page Frame
A page frame is a 4K-byte unit of contiguous addresses of physical main memory. Page
frames begin on 4K-byte boundaries and are fixed in size. A page is the collection of
data that occupies a page frame when that data is present in main memory or occupies
some location in secondary storage when there is not sufficient space in main memory.
4.2.2 Virtual Address
A virtual address refers indirectly to a physical address by specifying a page table, a page
within that table, and an offset within that page. Figure 4-3 shows the format of a virtual
address.
Figure 4-4 shows how the i860 microprocessor converts the DIR, PAGE, and OFFSET
fields of a virtual address into the physical address by consulting two levels of page
tables. The addressing mechanism uses the DIR field as an index into a page directory,
uses the PAGE field as an index into the page table determined by the page directory,
and uses the OFFSET field to address a byte within the page determined by the page
table.
4.2.3 Page Tables
A page table is simply an array of 32-bit page specifiers. A page table is itself a page, and
therefore contains 4 Kilobytes of memory or at most 1K 32-bit entries.
Two levels of tables are used to address a page of memory. At the higher level is a page
directory. The page directory addresses up to 1K page tables of the second level. A page
table of the second level addresses up to 1K pa:ffies. All the tables addressed by one page
directory, therefore, can address 1M pages (2 ). Because each page contains 4Kbytes
(212 bytes), the tables of one page directory can span the entire physical address space of
the i860 microprocessor (2 20 x 212
=
2 32 ).
DIR
r
PAGE OFFSET
240329i
Figure 4-3. Format of a Virtual Address
4-3