Figure D-8. Tc (Trace Controls) Register; Figure D-9. Bpcon (Breakpoint Control) Register - Intel i960 Jx Developer's Manual

REGISTER AND DATA STRUCTURES
Trace Mode Bits
Instruction Trace Mode - TC.i
Branch Trace Mode - TC.b
Call Trace Mode -TC.c
Return Trace Mode - TC.r
Pre-Return Trace Mode - TC.p
Supervisor Trace Mode - TC.s
Mark Trace Mode - TC.mk
31 28 24
d d i i
1 0 1 0
f f f f
Reserved
Section 9.1.1, "Trace Controls (TC) Register" (pg. 9-2)
DAB0
DAB1
m
1
28 24
31
Reserved
(Initialize to 0)

Figure D-9. BPCON (Breakpoint Control) Register

Section 9.2.7.4, "Breakpoint Control Register" (pg. 9-7)
D-10
20 16
Hardware Breakpoint Event Flags
Instruction-Address Breakpoint 0 - TC.i0f
Instruction-Address Breakpoint 1 - TC.i1f
Data-Address Breakpoint 0 - TC.d0f
Data-Address Breakpoint 1 - TC.d1f

Figure D-8. TC (Trace Controls) Register

m e e m m e e
0 1 0 1 0 1 0
20 16
12
m
s p r c b
k
12 8 4
8 4
Hardware Reset Value: 0000 0000H
Software Re-Init Value: 0000 0000H
i
0
0