Figure 14-3. Non-Burst Read And Write Transactions Without Wait States, 32-Bit Bus - Intel i960 Jx Developer's Manual

EXTERNAL BUS
Ta
CLKIN
AD31:0
ADDR
ALE
ADS
A3:2
BE3:0
WIDTH1:0
D/C
W/R
BLAST
DT/R
DEN
RDYRCV

Figure 14-3. Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus

14-10
Idle
Read
Td Tr Ti Ti Ta
D
Invalid
ADDR
In
10
Write
Idle
Td Tr Ti Ti
DATA Out
10
F_JF030A