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INITIALIZATION AND SYSTEM REQUIREMENTS
Example 12-1. Processor Initialization Flow
Processor_Initialization_flow()
{
FAIL_pin = true;
restore_full_cache_mode; disable(I_cache); invalidate(I_cache);
disable(D_cache); invalidate(D_cache);
BCON.ctv = 0; /* Selects PMCON14_15 to control all accesses */
PMCON14_15 = 0; /* Selects 8-bit bus width */
/** Exit Reset State & Start_Init **/
if (STEST_ON_RISING_EDGE_OF_RESET)
status = BIST();
FAIL_pin = false;
PC = 0x001f2002;
ibr_ptr = 0xfeffff30;
/** Read PMCON14_15 image in IBR **/
FAIL_pin = true;
DLMCON.dcen = 0;
PMCON14_15[byte2] = 0xc0 & memory[ibr_ptr + 8];
DLMCON.be = (memory[ibr_ptr + 0xc] >> 7);
/** Compute CheckSum on Boot Record **/
carry = 0;
CheckSum = 0xffffffff;
for (i=0; i<8; i++) /* carry is carry out from previous add*/
CheckSum = memory[ibr_ptr + 16 + i*4] + CheckSum + carry;
if (CheckSum != 0)
{ fail_msg = 0xfeffff64;
dummy = memory[fail_msg];
for (;;) ;
}
else
FAIL_pin = false;
/** Process PRCB **/
prcb_ptr
= memory[ibr_ptr+0x14];
Process_PRCB(prcb_ptr);
IP = memory[ibr_ptr+0x10];
g0 = DEVICE_ID;
return;/* Execute First Instruction */
}
Bit 31 of the assembled PMCON word loaded from the IBR is written to DLMCON.be to
establish the initial endianism of memory; the processor initializes the DLMCON.dcen bit to 0 to
disable data caching. The remainder of the assembled word is used to initialize PMCON14_15. In
conjunction with this step, the processor clears the bus control table valid bit (BCON.ctv), to
ensure for the remainder of initialization that every bus request issued takes configuration
information from the PMCON14_15 register, regardless of the memory region associated with the
request. At a later point in initialization, the processor loads the remainder of the memory region
12-14
/* BIST does not return if it fails */
/* PC.Priority = 31, PC.em = Supervisor,*/
/* PC.te = 0; PC.State = Interrupted
/* ibr_ptr used to fetch IBR words
IMSK
= 0;
LMMR0.lmte = 0;
LMMR1.lmte = 0;
/* Fail BUS Confidence Test */
/* Do load with address = fail_msg */
/* loop forever with FAIL pin true */
/* See Process PRCB Section for Details */
*/
*/
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