Table of Contents
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CHAPTER 3
PROGRAMMING ENVIRONMENT
3.1
OVERVIEW ................................................................................................................... 3-1
3.2
REGISTERS AND LITERALS AS INSTRUCTION OPERANDS................................... 3-1
3.2.1
Global Registers ...................................................................................................... 3-2
3.2.2
Local Registers ........................................................................................................ 3-3
3.2.3
Register Scoreboarding ........................................................................................... 3-4
3.2.4
Literals ..................................................................................................................... 3-4
3.2.5
Register and Literal Addressing and Alignment ....................................................... 3-4
3.3
MEMORY-MAPPED CONTROL REGISTERS.............................................................. 3-6
3.3.1
Memory-Mapped Registers (MMR) ......................................................................... 3-6
3.3.1.1
Restrictions on Instructions that Access Memory-Mapped Registers .............. 3-6
3.3.1.2
Access Faults ................................................................................................... 3-7
3.4
ARCHITECTURALLY DEFINED DATA STRUCTURES ............................................. 3-11
3.5
MEMORY ADDRESS SPACE..................................................................................... 3-13
3.5.1
Memory Requirements .......................................................................................... 3-14
3.5.2
Data and Instruction Alignment in the Address Space .......................................... 3-15
3.5.3
Byte, Word and Bit Addressing .............................................................................. 3-15
3.5.4
Internal Data RAM ................................................................................................. 3-16
3.5.5
Instruction Cache ................................................................................................... 3-16
3.5.6
Data Cache ............................................................................................................ 3-17
3.6
LOCAL REGISTER CACHE........................................................................................ 3-17
3.7
PROCESSOR-STATE REGISTERS ........................................................................... 3-17
3.7.1
Instruction Pointer (IP) Register ............................................................................ 3-17
3.7.2
Arithmetic Controls (AC) Register .......................................................................... 3-18
3.7.2.1
Initializing and Modifying the AC Register ...................................................... 3-18
3.7.2.2
Condition Code (AC.cc) .................................................................................. 3-19
3.7.3
Process Controls (PC) Register ............................................................................. 3-21
3.7.3.1
Initializing and Modifying the PC Register ...................................................... 3-22
3.7.4
Trace Controls (TC) Register ................................................................................. 3-23
3.8
USER-SUPERVISOR PROTECTION MODEL ........................................................... 3-23
3.8.1
Supervisor Mode Resources ................................................................................. 3-23
3.8.2
Using the User-Supervisor Protection Model ......................................................... 3-24
CHAPTER 4
CACHE AND ON-CHIP DATA RAM
4.1
INTERNAL DATA RAM ................................................................................................. 4-1
4.2
4.3
BIG ENDIAN ACCESSES TO INTERNAL RAM AND DATA CACHE........................... 4-4
4.4
4.4.1
Enabling and Disabling the Instruction Cache ......................................................... 4-4
4.4.2
Operation While the Instruction Cache Is Disabled ................................................. 4-5
4.4.3
Loading and Locking Instructions in the Instruction Cache ..................................... 4-5
iv
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