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8.6
MULTIPLE AND PARALLEL FAULTS
Multiple fault conditions can occur during a single instruction execution and during multiple
instruction execution when the instructions are executed by different units within the processor.
The following sections describe how faults are handled under these conditions.
8.6.1
Multiple Non-Trace Faults on the Same Instruction
Multiple fault conditions can occur during a single instruction execution. For example, an instruction
can have an invalid operand and unaligned address. When this situation occurs, the processor is
required to recognize and generate at least one of the fault conditions. The processor may not detect
all fault conditions and will report only one detected non-trace fault on a single instruction.
In a multiple fault situation, the reported fault condition is left to the implementation.
8.6.2
Multiple Trace Fault Conditions on the Same Instruction
Trace faults on different instructions cannot happen concurrently, because trace faults are precise
(see
section 8.9, "PRECISE AND IMPRECISE FAULTS" (pg.
conditions on the same instruction are reported in a single trace fault record (with the exception of
prereturn trace, which always happens alone). To support multiple fault reporting, the trace fault
uses bit positions in the fault-subtype field to indicate occurrences of multiple faults of the same
type (see
Table
8-1).
8.6.3
Multiple Trace and Non-Trace Fault Conditions on the Same Instruction
The execution of a single instruction can create one or more trace fault conditions in addition to
multiple non-trace fault conditions. When this occurs:
•
The pending trace is dismissed if any of the non trace faults dismisses it, as mentioned in the
"Trace Reporting" paragraph for that fault in
•
The processor services one of the non trace faults.
•
Finally, the trace is serviced upon return from the non-trace fault handler if it was not
dismissed in step 1.
8.6.4
Parallel Faults
The i960 Jx processor exploits the architecture's tolerance of out-of-order instruction execution by
issuing instructions to independent execution units on the chip. The following subsections describe
how the processor handles faults in this environment.
8-19)). Multiple trace fault
section 8.10, "FAULT REFERENCE" (pg.
FAULTS
8
8-21).
8-9
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