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INSTRUCTION SET REFERENCE
Table 6-12. DCCTL Status Values and D-Cache Parameters
Value
bytes per atom
atoms per line
number of sets
number of ways
cache size
Status[0] (enable / disable)
Status[1:3] (reserved)
Status[7:4] (log
(bytes per atom))
2
Status[11:8] (log
(atoms per line))
2
Status[15:12] (log
(number of
2
sets))
Status[27:16] (number of ways - 1)
Figure 6-2. Store Data Cache to Memory Output Format
6-42
Value on
i960JA CPU
4
4
64
1 (Direct)
1-Kbytes
0 or 1
0
2
2
6
0
0
Tag (Starting set)
Valid Bits (Starting set)
Word 0
Word 1
Word 2
Word 3
0
Tag (Starting set + 1)
Valid Bits (Starting set + 1)
. . .
Value on
Value on
i960JD/JF
i960JT CPU
CPU
4
4
4
4
128 (full)
256
1 (Direct)
1 (Direct)
2-Kbytes(full)
4-Kbytes
0 or 1
0 or 1
0
0
2
2
2
2
7 (full)
8 (full)
0
0
Destination
Address
(DA)
DA + 4H
DA + 8H
DA + CH
DA + 10H
DA + 14H
DA + 18H
DA + 1CH
DA + 20H
DA + 24H
. . .
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