Table of Contents
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INDEX
comparison instructions, overview
compare and increment or decrement instructions
5-13
5-13
test condition instructions
6-38
concmpi
6-38
concmpo
conditional branch instructions
5-17
conditional fault instructions
,
3-1
3-7
control registers
3-6
memory-mapped
1-6
overview
,
,
3-1
3-7
3-12
control table
3-15
alignment
Control Table Valid (CTV) bit
core architecture
A-1
and software portability
D
9-10
DAB
Data Address Breakpoint (DAB) Register Format
9-10
Data Address Breakpoint (DAB) registers
9-8
programming
data alignment in external memory
data cache
cache coherency and non-cacheable accesses
coherency
4-10
I/O and bus masters
6-40
control instruction
4-6
described
4-6
enabling and disabling
,
1-4
4-8
fill policy
1-4
overview
partial-hit multi-word data accesses
4-10
visibility
4-8
write policy
Data Cache Enable (DCEN) bit
A-7
data control peripheral units
5-5
data movement instructions
5-6
load address instruction
5-5
load instructions
5-6
move instructions
3-16
data RAM
Data Register
Index-4
timing diagram
data structures
control table
fault table
Initialization Boot Record (IBR)
interrupt stack
3-19
interrupt table
literals
local stack
Process Control Block (PRCB)
supervisor stack
system procedure table
user stack
13-6
data types
bits and bit fields
integers
literals
ordinals
supported
triple and quad words
dcctl
9-9
DCEN bit, see Data Cache Enable (DCEN) bit
debug
3-15
overview
debug instructions
4-9
decoupling capacitors
Default Logical Memory Configuration (DLMCON)
DLMCON.be bit
design considerations
high frequency
interference
latchup
4-7
line termination
Device ID register
device ID Register
13-12
device ID register
DEVICEID register location
6-47
divi
divide integer instruction
divide ordinal instruction
6-47
divo
DLMCON registers
15-18
,
,
3-1
3-7
3-12
,
3-1
3-12
3-1
,
3-1
3-12
,
3-1
3-12
3-4
3-1
3-1
,
3-1
3-12
,
3-1
3-12
3-12
2-3
2-2
2-4
2-2
2-1
2-3
,
,
,
4-6
4-10
6-40
3-23
9-1
5-18
12-36
13-3
register
4-4
12-38
12-40
12-39
12-38
15-6
12-22
D-23
3-3
6-47
6-47
,
3-11
,
3-11
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