Intel i960 Jx Developer's Manual page 177

Example:
icctl g0,g1,g2
Opcode: icctl
See Also: sysctl
This instruction is implemented on the 80960Rx, 80960Hx and 80960Jx pro-
Notes:
cessor families only, and may or may not be implemented on future i960 pro-
cessors.
INSTRUCTION SET REFERENCE
# g0 = 3, g1=0x10000000, g2=1
# Load and lock 1 block of cache
# (one way) with
# location of code at starting
# 0x10000000.
65BH REG
6
6-65