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EXTERNAL BUS
14.2.3.5
Recovery States
The state following the last data transfer of an access is a recovery (Tr) state. By default, i960 Jx
microprocessor bus transactions have one recovery state. External logic can cause additional
recovery states to be inserted by driving the RDYRCV pin low at the end of Tr.
Recovery wait states are an important feature for the Jx because it employs a multiplexed bus.
Slow memory and I/O devices often need a long time to turn off their output drivers on read
accesses before the microprocessor drives the address for the next bus access. Recovery wait states
are also useful to force a delay between back-to-back accesses to I/O devices with their own
specific access recovery requirements.
System ready logic is often described as normally-ready or normally-not-ready. Normally-ready
logic asserts a microprocessor's input pin during all bus states, except when wait states are desired.
Normally-not-ready logic deasserts a processor's input pin during all bus states, except when the
processor is ready. The subtle nomenclature distinction is important for i960 Jx microprocessor
systems because the active sense of the RDYRCV pin reverses for recovery states. During the Tr
state, logic 0 means "continue to recover" or "not ready"; for Tw/Td states, logic 0 means "ready".
Logic must assure "ready" and "not recover" are generated to terminate an access properly. Be
certain to not hang the processor with endless recovery states. Conventional ready logic implemented
as normally-not-ready will operate correctly (but without adding turnaround wait states).
Figure 14-12
is a timing waveform of a read cycle followed by a write cycle, with an extra
recovery state inserted into the read cycle.
14
14-19
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