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configuration table from the external control table. The Bus Configuration (BCON) register is also
loaded at this time. The control table valid (BCON.ctv) bit is then set in the control table to
validate the PMCON registers after they are loaded. In this way, the bus controller is completely
configured during initialization. (See
of memory regions and configuring the bus controller.)
After the bus configuration data is loaded and the new bus configuration is in place, the processor
loads the remainder of the IBR which consists of the first instruction pointer, the PRCB pointer and
six checksum words. The PRCB pointer and the first instruction pointer are internally cached. The
six checksum words — along with the PRCB pointer and the first instruction pointer — are used in
a checksum calculation which implements a confidence test of the external bus. The checksum
calculation is shown in the pseudo-code flow in
zero, then the confidence test of the external bus passes.
Figure 12-4
further describe the IBR organization.
byte 3
28
24
PMCON14_15 Register
Reserved
(Initialize to 0)
Figure 12-5. PMCON14_15 Register Bit Description in IBR
INITIALIZATION AND SYSTEM REQUIREMENTS
CHAPTER 14, EXTERNAL BUS
Example
12-1. If the checksum calculation equals
Boot Bit Endian (BBGE)
(0) Little Endian
(1) Big Endian
Bus Width (BW)
(00) 8-bit
(01) 16-bit
(10) 32-bit
(11) Reserved
byte 1
byte 2
20
16
12
for a complete discussion
byte 0
8
4
0
12-15
12
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