Table 3-6. Data Structure Descriptions - Intel i960 Jx Developer's Manual

Microprocessor
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PROGRAMMING ENVIRONMENT
Structure (see also)
User and Supervisor Stacks
section 7.6, "USER AND
SUPERVISOR STACKS"
(pg. 7-19)
Interrupt Stack
section 11.5, "INTERRUPT
STACK AND INTERRUPT
RECORD" (pg. 11-7)
System Procedure Table
section 3.8, "USER-SUPER-
VISOR PROTECTION MODEL"
(pg. 3-23)
section 7.5, "SYSTEM CALLS"
(pg. 7-15)
Interrupt Table
section 11.4, "INTERRUPT
TABLE" (pg. 11-4)
Fault Table
section 8.3, "FAULT TABLE"
(pg. 8-4)
Control Table
section 12.3.3, "Control Table"
(pg. 12-20)
3-12

Table 3-6. Data Structure Descriptions

The processor uses these stacks when executing application
code.
A separate interrupt stack is provided to ensure that interrupt
handling does not interfere with application programs.
Contains pointers to system procedures. Application code uses
the system call instruction (calls) to access system procedures
through this table. A system supervisor call switches execution
mode from user mode to supervisor mode. When the
processor switches modes, it also switches to the supervisor
stack.
The interrupt table contains vectors (pointers) to interrupt
handling procedures. When an interrupt is serviced, a
particular interrupt table entry is specified.
Contains pointers to fault handling procedures. When the
processor detects a fault, it selects a particular entry in the fault
table. The architecture does not require a separate fault
handling stack. Instead, a fault handling procedure uses the
supervisor stack, user stack or interrupt stack, depending on
the processor execution mode in which the fault occurred and
the type of call made to the fault handling procedure.
Contains on-chip control register values. Control table values
are moved to on-chip registers at initialization or with sysctl.
Description

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