Figure 14-8. Burst Read And Write Transactions W/O Wait States, 32-Bit Bus - Intel i960 Jx Developer's Manual

T T
a d
CLKIN
AD31:0 ADDR
ALE
ADS
00 or 01
A3:2
BE3:0
WIDTH1:0
D/C
W/R
BLAST
DT/R
DEN
RDYRCV

Figure 14-8. Burst Read and Write Transactions w/o Wait States, 32-bit Bus

T T T T T
d r a d d
D DATA DATA DATA
D
ADDR
In
In Out Out
01 or 11 00 01
1 0
1 0
EXTERNAL BUS
T T T
d d r
DATA
Out
Out
10 11
14
14-15