Table of Contents
Advertisement
Instruction Cache
A memory array used for temporary storage of instructions fetched from
main memory. Its purpose is to streamline instruction execution by
reducing the number of instruction fetches required to execute a program.
Instruction Pointer
A 32-bit register that contains the address (in the address space) of the
(IP)
instruction currently being executed. Since instructions are required to be
aligned on word boundaries in memory, the IP's two least-significant bits
are always zero.
Integer Overflow
AC register bit 8. When integer overflow faults are masked, the processor
Flag
sets the integer overflow flag whenever integer overflow occurs to
indicate that the fault condition has occurred even though the fault has
been masked. If the fault is not masked, the fault is allowed to occur and
the flag is not set.
Integer Overflow
AC register bit 12. This bit masks the integer overflow fault.
Mask Bit
Interrupt Call
An implicit call to a interrupt handling procedure. The processor
performs interrupt calls automatically without any intervention from
software. It gets vectors (pointers) to interrupt handling procedures from
the interrupt table.
Interrupt Stack
Stack the processor uses when it executes interrupt handling procedures.
Interrupt Table
A data structure that contains vectors to interrupt handling procedures and
fields for storing pending interrupts. When the processor receives an
interrupt, it uses the vector number that accompanies the interrupt to
locate an interrupt vector in the interrupt table. The interrupt table's
pending interrupt fields contain bits that indicate priorities and vector
numbers of interrupts waiting to be serviced.
Interrupt Vector
A pointer to an interrupt handling procedure. In the i960 architecture,
interrupts vectors are stored in the interrupt table.
Interrupt
An event that causes program execution to be suspended temporarily to
allow the processor to handle a more urgent chore.
Leaf Procedure
Leaf procedures call no other procedures. They are called "leaf
procedures" because they reside at the "leaves" of the call tree.
Literals
A set of 32 ordinal values ranging from 0 to 31 (5 bits) that can be used as
operands in certain instructions.
Little Endian
The bus controller reads or writes a data word's least-significant byte to
the bus' eight least-significant data lines (D7:0). Little endian systems
store a word's least-significant byte at the lowest byte address in memory.
For example, if a little endian ordered word is stored at address 600, the
least-significant byte is stored at address 600 and the most-significant
byte at address 603. Compare with big endian.
GLOSSARY
Glossary-3
Advertisement
Table of Contents
