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The i960 JA processor has a 2-Kbyte instruction cache; the JF and JD have a 4-Kbyte instruction
cache; the 80960JT has a 16-Kbyte instruction cache. The instruction cache is purged using the
system control (
) or instruction cache control (
sysctl
available on all i960 processors.
An
icctl
or
sysctl
instruction is issued with a configure-instruction-cache message type to select
the load-and-lock mechanism. When the lock option is selected, the processor loads the cache
starting at an address specified as an operand to the instruction.
The instruction cache supports locking code into half of the cache. The unlocked portion functions
as a direct-mapped cache. Refer to
description of cache configuration.
The i960 JA processor has a 1-Kbyte data cache; the i960 JF and JD processors have a 2-Kbyte
data cache and the 80960JT has a 4-Kbyte data cache. With respect to data accesses on a
region-by-region basis, external memory is configured as either cacheable or non-cacheable. A bit
in the memory region table entry defines whether or not data accesses are cacheable. This makes it
very easy to partition a system into non-cacheable regions (for I/O or shared data in a
multiprocessor system) and cacheable regions (local system memory) with no external hardware
logic. To maintain data cache coherency, the i960 Jx processor implements a simple single
processor coherency mechanism. Also, by software control, the data cache can be globally
enabled, globally disabled or globally invalidated. A data access is either:
•
Explicitly defined as cacheable or non-cacheable—through the memory region table
•
Implicitly defined as non-cacheable—by the nature of the access; all atomic accesses
(
atmod
,
atadd
) are implicitly defined as non-cacheable data accesses
The data cache indirectly supports unaligned accesses. Microcode execution breaks unaligned
accesses into aligned accesses that are cacheable or non-cacheable according to the same rules as
aligned accesses. An unaligned access could be only partially in the data cache and be a combination
of hits and misses. The data cache supports both big-endian and little-endian data types.
A.3
Data and Data Structure Alignment
The i960 architecture does not define how to handle loads and stores to non-aligned addresses.
Therefore, code that generates non-aligned addresses may not be compatible with all i960
processor implementations. The i960 Jx processor automatically handles non-aligned load and
store requests in microcode.
The address boundaries on which an operand begins can affect processor performance. Operands
that span more word boundaries than necessary suffer a cost in speed due to extra bus cycles.
CONSIDERATIONS FOR WRITING PORTABLE CODE
) instruction. These instructions are not
icctl
section 4.4, "INSTRUCTION CACHE" (pg. 4-4)
A
for a
A-3
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