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10.3
TIMER INTERRUPTS
Each timer is the source for one interrupt. When a timer detects a zero count in its TCRx, the timer
generates an internal edge-detected Timer Interrupt signal (TINTx) to the interrupt controller, and
the interrupt-pending (IPND.tipx) bit is set in the interrupt controller. Each timer interrupt can be
selectively masked in the Interrupt Mask (IMSK) register or handled as a dedicated
hardware-requested interrupt. Refer to
hardware-requested interrupts.
When the interrupt is disabled after a request is generated, but before a pending interrupt is
serviced, the interrupt request is still active (the Interrupt Controller latches the request). When a
timer generates a second interrupt request before the CPU services the first interrupt request, the
second request may be lost.
When auto-reload is enabled for a timer, the timer continues to decrement the value in TCRx even
after entry into the timer interrupt handler.
10.4
POWERUP/RESET INITIALIZATION
Upon power up, external hardware reset or software reset (
initialized to the values shown in
Table 10-6. Timer Powerup Mode Settings
Mode/Control Bit
TMRx.tc = 0
TMRx.enable = 0
TMRx.reload = 0
TMRx.sup = 0
TMRx.csel1:0 = 0
TCRx.d31:0 = 0
TRRx.d31:0 = 0
TINTx output
CHAPTER 11, INTERRUPTS
Table
10-6.
No terminal count
Prevents counting and assertion of TINTx
Single terminal count mode
Supervisor or user mode access
Timer Clock = Bus Clock
Undefined
Undefined
Deasserted
TIMERS
for a description of
sysctl
), the timer registers are
Notes
10
10-11
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