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INTERRUPTS
Figure 11-7
shows how a signal is sampled in each mode. The debounce-sampling option adds
several clock cycles to an interrupt's latency due to the multiple clocks of sampling. Inputs are
sampled once every CLKIN cycle (external bus clock).
Interrupt pins are asynchronous inputs. Setup or hold times relative to CLKIN are not needed to
ensure proper pin detection. Note in
CLKIN cycles. For practical purposes, this means that asynchronous interrupting devices must
generate an interrupt signal that is asserted for at least three CLKIN cycles for the fast sampling
mode or seven CLKIN cycles for the debounce sampling mode. See
Documents" (pg.
1-10). These documents have setup and hold specifications that guarantee
detection of the interrupt on particular edges of CLKIN. These specification are useful in designs
that use synchronous logic to generate interrupt signals to the processor. These specification must
also be used to calculate the minimum signal width, as shown in
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CLKIN
XINT[7:0]
(fast sampled)
XINT[7:0]
(debounce)
Denotes sampling clock edge. Interrupt pins are sampled every CLKIN (external bus clock) cycle.
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11-20
Figure 11-7
that interrupt inputs are sampled once every two
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*
*
2 cycle min.
Detect
Interrupt
4 cycle min.
Detect
Interrupt
Figure 11-7. Interrupt Sampling
section 1.4, "Related
Figure
11-7.
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