Table of Contents
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INDEX
6-55
fmark
6-55
force mark instruction
FP, see Frame Pointer
7-7
frame fills
7-4
Frame Pointer (FP)
3-3
location
7-7
frame spills
G
,
3-1
3-2
global registers
1-9
overview
H
,
6-56
3-23
halt
6-56
halt CPU instruction
hardware breakpoint resources
9-6
requesting access privilege
4-3
high priority interrupts
14-32
HOLD/HOLDA protocol
I
IBR, see initialization boot record
,
,
,
,
1-4
4-4
4-5
4-6
3-23
icctl
11-22
ICON
IEEE Standard Test Access Port
15-2
IEEE Std. 1149.1
11-24
IMAP0-IMAP2
,
12-1
12-10
IMI
implementation-specific features
,
7-1
8-2
implicit calls
5-24
imprecise faults
11-26
IMSK
index with displacement addressing mode
3-14
indivisible access
inequalities (greater than, equal or less than)
3-19
conditions
12-1
Initial Memory Image (IMI)
12-10
initial memory image (IMI)
,
12-1
12-2
initialization
12-34
CLKIN
12-23
code example
12-34
hardware requirements
12-23
MON960
12-34
power and ground
6-114
software
Index-6
Initialization Boot Record (IBR)
alignment
initialization data structures
initialization mechanism
initialization requirements
architecture reserved memory space
control table
data structures
Process Control Block
Instruction Breakpoint (IBP) registers
Instruction Breakpoint (IPB) Register Format
instruction breakpoint modes
programming
instruction cache
9-5
coherency
configuration
enabling and disabling
locking instructions
overview
visibility
,
A-3
instruction formats
assembly language format
instruction encoding format
15-2
instruction optimizations
Instruction Pointer (IP) Register
Instruction Pointer (IP) register
A-1
Instruction Register (IR)
timing diagram
Instruction set
atmod
2-8
sysctl
instruction set
6-7
ADD 6-7
addc
addi
addie
addig
addige
addil
addile
addine
addino
,
3-1
,
12-13
12-15
3-15
3-11
A-5
,
12-21
D-22
12-10
12-16
9-11
3-16
4-5
3-16
,
4-4
12-19
4-5
1-4
4-5
5-3
5-1
5-2
5-20
3-17
3-17
,
15-2
15-5
15-17
3-8
3-8
6-10
6-11
6-7
6-7
6-7
6-7
6-7
6-7
6-7
,
,
3-11
12-1
12-9
9-10
9-10
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