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Table 3-5. User Space Family Registers and Tables
Register Name
Timers
Reserved
(TRR0) Timer Reload Register 0
(TCR0) Timer Count Register 0
(TMR0) Timer Mode Register 0
Reserved
(TRR1) Timer Reload Register 1
(TCR1) Timer Count Register 1
(TMR1) Timer Mode Register 1
Reserved
3.4
ARCHITECTURALLY DEFINED DATA STRUCTURES
The architecture defines a set of data structures including stacks, interfaces to system procedures,
interrupt handling procedures and fault handling procedures.
and references other sections of this manual where detailed information can be found.
The i960 Jx processor defines two initialization data structures: the Initialization Boot Record
(IBR) and the Process Control Block (PRCB). These structures provide initialization data and
pointers to other data structures in memory. When the processor is initialized, these pointers are
read from the initialization data structures and cached for internal use.
Pointers to the system procedure table, interrupt table, interrupt stack, fault table and control table
are specified in the processor control block. Supervisor stack location is specified in the system
procedure table. User stack location is specified in the user's startup code. Of these structures, only
the system procedure table, fault table, control table and initialization data structures may be in
ROM; the interrupt table and stacks must be in RAM. The interrupt table must be located in RAM
to allow posting of software interrupts.
PROGRAMMING ENVIRONMENT
Memory-Mapped
Access Type
Address
FF00 0000H to
FF00 02FFH
FF00 0300H
FF00 0304H
FF00 0308H
FF00 030CH
FF00 0310H
FF00 0314H
FF00 0318H
FF00 031CH to
FF00 7FFFH
Table 3-6
defines the data structures
3
—
R/W
R/W
R/W
—
R/W
R/W
R/W
—
3-11
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