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13.6.5
Initialization
Immediately following a hardware reset, all LMTs are disabled. The LMTE bit in each of the
LMMR registers is cleared (0) and all other bits are undefined. Immediately after a hardware reset
the Default Logical Memory Control register (DLMCON) has the values shown in
DLMCON Bit
DCEN (Data Caching Enable) 0 (Data Caching Disabled)
BE (Big-Endian)
Application software may initialize and enable the logical memory template after hardware reset.
After a software re-initialization, the DLMCON.be retains its value and DLMCON.dcen is cleared.
13.6.6
Boundary Conditions for Logical Memory Templates
The following sections describe the operation of the LMT registers during conditions other than
"normal" accesses. See
CHAPTER 4, CACHE AND ON-CHIP DATA RAM
data cache coherency when modifying an LMT.
13.6.6.1
Internal Memory Locations
The LMT registers are not used during accesses to memory-mapped registers. Internal data RAM
locations are never cached; LMT bits controlling caching are ignored for data RAM accesses.
However, the byte-ordering of the internal data RAM is controlled by DLMCON.be.
13.6.6.2
Overlapping Logical Data Template Ranges
Logical data templates that specify overlapping ranges are not allowed. When an access is attempted
that matches more than one enabled LMT range, the operation of the access becomes undefined.
To establish different logical memory attributes for the same address range, program
non-overlapping logical ranges, then use partial physical address decoding.
Table 13-2. DLMCON Values at Reset
Value Upon
Hardware Reset
Initialized from PMCON14_15
image in IBR bit 31
MEMORY CONFIGURATION
Table
Value Upon
Software Re-initialization
0 (Data Caching Disabled)
Value before software
re-initialization
for a treatment of
13-2.
13
13-13
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