Intel PXA255 Manuals

Manuals and User Guides for Intel PXA255. We have 3 Intel PXA255 manuals available for free PDF download: Developer's Manual, User Manual, Datasheet

Intel PXA255 Developer's Manual (600 pages)

Intel Computer Hardware User Manual

Brand: Intel | Category: Computer Hardware | Size: 5.41 MB

Table of Contents
3
Revision History
23
1 Introduction

25
- Intel Xscale® Microarchitecture Features
  25
- System Integration Features
  25
  - Memory Controller
    26
  - Clocks and Power Controllers
    26
  - Universal Serial Bus (USB) Client
    26
  - DMA Controller (DMAC)
    27
  - LCD Controller
    27
  - AC97 Controller
    27
  - Inter-IC Sound (I2S) Controller
    27
  - Multimedia Card (MMC) Controller
    27
  - Fast Infrared (FIR) Communication Port
    27
  - Synchronous Serial Protocol Controller (SSPC)
    28
  - Gpio
    28
  - Uarts
    28
  - Real-Time Clock (RTC)
    29
  - OS Timers
    29
  - Pulse-Width Modulator (PWM)
    29
  - Interrupt Control
    29
  - Network Synchronous Serial Protocol Port
    29
2 System Architecture

31
3 Clocks and Power Manager

63
4 System Integration Unit

105
- General-Purpose I/O
  105
  - GPIO Operation
    105
  - GPIO Alternate Functions
    106
- General-Purpose I/O Block Diagram
  106
  - GPIO Alternate Functions
    107
  - GPIO Register Definitions
    110
- GPLR0 Bit Definitions
  111
- GPLR1 Bit Definitions
  112
- GPLR2 Bit Definitions
  112
- GPDR0 Bit Definitions
  113
- GPDR1 Bit Definitions
  113
- GPDR2 Bit Definitions
  113
- GPSR0 Bit Definitions
  114
- GPSR1 Bit Definitions
  114
- GPSR2 Bit Definitions
  115
- GPCR0 Bit Definitions
  115
- GPCR1 Bit Definitions
  115
- GPCR2 Bit Definitions
  116
- GRER0 Bit Definitions
  117
- GRER1 Bit Definitions
  117
- GRER2 Bit Definitions
  117
- GFER0 Bit Definitions
  118
- GFER1 Bit Definitions
  118
- GFER2 Bit Definitions
  118
- GEDR0 Bit Definitions
  119
- GEDR1 Bit Definitions
  119
- GEDR2 Bit Definitions
  120
- GAFR0_L Bit Definitions
  121
- GAFR0_U Bit Definitions
  121
- GAFR1_L Bit Definitions
  122
- GAFR1_U Bit Definitions
  122
- GAFR2_L Bit Definitions
  123
- GAFR2_U Bit Definitions
  123
  - Interrupt Controller
    124
    
    Interrupt Controller Operation
    124
    
    Interrupt Controller Register Definitions
    125
- Interrupt Controller Block Diagram
  125
- ICMR Bit Definitions
  126
- ICLR Bit Definitions
  127
- ICCR Bit Definitions
  127
- ICIP Bit Definitions
  128
- ICFP Bit Definitions
  128
- ICPR Bit Definitions
  129
- List of First–Level Interrupts
  131
  - Real-Time Clock (RTC)
    132
    
    Real-Time Clock Operation
    132
    
    RTC Register Definitions
    133
- RTTR Bit Definitions
  134
- RTAR Bit Definitions
  134
- RCNR Bit Definitions
  135
  - Trim Procedure
    136
- RTSR Bit Definitions
  136
  - Operating System (OS) Timer
    138
    
    OS Timer Register Definitions
    139
    
    Watchdog Timer Operation
    139
- Osmr[X] Bit Definitions
  140
- OIER Bit Definitions
  140
- OWER Bit Definitions
  141
- OSCR Bit Definitions
  141
  - Pulse Width Modulator
    142
    
    Pulse Width Modulator Operation
    142
- OSSR Bit Definitions
  142
- Pwmn Block Diagram
  143
  - Register Descriptions
    144
- Pwm_Ctrln Bit Definitions
  145
- Pwm_Dutyn Bit Definitions
  146
  - Pulse Width Modulator Output Wave Example
    147
- Basic Pulse Width Waveform
  147
- Pwm_Pervaln Bit Definitions
  147
  - System Integration Unit Register Summary
    148
    
    GPIO Register Locations
    148
- GPIO Register Addresses
  148
- RTC Register Addresses
  149
- OS Timer Register Addresses
  149
  - Pulse Width Modulator Register Locations
    150
  - Pulse Width Modulator Register Addresses
    150
5 DMA Controller

151
- DMA Description
  151
- DMAC Block Diagram
  151
  - DMAC Channels
    152
  - Signal Descriptions
    152
- DMAC Signal List
  152
  - DMA Channel Priority Scheme
    153
- DREQ Timing Requirements
  153
- Channel Priority
  154
  - DMA Descriptors
    155
- Priority Schemes Examples
  155
- No-Descriptor Fetch Mode Channel State
  156
  - Channel States
    158
- Descriptor Fetch Mode Channel State
  158
  - Read and Write Order
    159
  - Byte Transfer Order
    159
  - Trailing Bytes
    160
- Little Endian Transfers
  160
  - Transferring Data
    161
    
    Servicing Internal Peripherals
    161
    
    Quick Reference for DMA Programming
    163
- DMA Quick Reference for Internal Peripherals
  163
  - Servicing Companion Chips and External Peripherals
    164
  - Memory-To-Memory Moves
    166
  - DMAC Registers
    167
    
    DMA Channel Control/Status Register (Dcsrx)
    167
    
    DMA Interrupt Register (DINT)
    167
- DINT Bit Definitions
  167
- Dcsrx Bit Definitions
  168
  - DMA Request to Channel Map Registers (Drcmrx)
    170
  - DMA Descriptor Address Registers (Ddadrx)
    170
- Drcmrx Bit Definitions
  170
  - DMA Source Address Registers
    171
- Ddadrx Bit Definitions
  171
  - DMA Target Address Registers (Dtadrx)
    172
- Dsadrx Bit Definitions
  172
  - DMA Command Registers (DCMDX)
    173
- Dtadrx Bit Definitions
  173
- DCMDX Bit Definitions
  174
  - Examples
    176
  - DMA Controller Register Summary
    178
6 Memory Controller

183
7 LCD Controller

265
- Overview
  265
  - Features
    266
  - LCD Controller Block Diagram
    267
  - Pin Descriptions
    268
- LCD Controller Operation
  268
  - Enabling the Controller
    268
  - Disabling the Controller
    269
  - Resetting the Controller
    269
- Detailed Module Descriptions
  269
  - Input Fifos
    269
  - Lookup Palette
    270
  - Temporal Modulated Energy Distribution (TMED) Dithering
    270
- Compare Range for TMED
  271
  - Output Fifos
    272
  - LCD Controller Pin Usage
    272
- TMED Block Diagram
  272
  - Dma
    273
  - LCD External Palette and Frame Buffers
    274
    
    External Palette Buffer
    274
    
    External Frame Buffer
    275
- Palette Buffer Format
  275
- Bit Per Pixel Data Memory Organization
  275
- Bits Per Pixel Data Memory Organization
  276
- Bits Per Pixel Data Memory Organization - Passive Mode
  277
- Bits Per Pixel Data Memory Organization - Active Mode
  277
  - Functional Timing
    278
- Passive Mode Start-Of-Frame Timing
  279
- Passive Mode End-Of-Frame Timing
  279
- Passive Mode Pixel Clock and Data Pin Timing
  280
- Active Mode Timing
  280
- Active Mode Pixel Clock and Data Pin Timing
  281
  - Register Descriptions
    281
    
    LCD Controller Control Register 0 (LCCR0)
    282
- Frame Buffer/Palette Output to LCD Data Pins in Active Mode
  284
- LCD Controller Data Pin Utilization
  285
- LCD Data-Pin Pixel Ordering
  286
- LCCR0 Bit Definitions
  287
  - LCD Controller Control Register 1 (LCCR1)
    288
  - LCD Controller Control Register 2 (LCCR2)
    290
- LCCR1 Bit Definitions
  290
  - LCD Controller Control Register 3 (LCCR3)
    292
- LCCR2 Bit Definitions
  292
- LCCR3 Bit Definitions
  295
  - LCD Controller DMA
    296
- Fdadrx Bit Definitions
  297
- Fsadrx Bit Definitions
  298
- Fidrx Bit Definitions
  298
- Ldcmdx Bit Definitions
  300
  - LCD DMA Frame Branch Registers (Fbrx)
    301
- Fbrx Bit Definitions
  301
  - LCD Controller Status Register (LCSR)
    302
- LCSR Bit Definitions
  304
  - LCD Controller Interrupt ID Register (LIIDR)
    305
- LIICR Bit Definitions
  305
  - TMED RGB Seed Register (TRGBR)
    306
- TRGBR Bit Definitions
  306
  - TMED Control Register (TCR)
    307
  - LCD Controller Register Summary
    308
- TCR Bit Definitions
  308
8 Synchronous Serial Port Controller

311
- Overview
  311
- Signal Description
  311
  - External Interface to Synchronous Serial Peripherals
    311
  - External Interface to Codec
    311
- Functional Description
  312
  - Data Transfer
    312
- Data Formats
  312
  - Serial Data Formats for Transfer To/From Peripherals
    312
- Texas Instruments' Synchronous Serial Frame* Format
  314
- Motorola SPI* Frame Format
  315
  - Parallel Data Formats for FIFO Storage
    316
- National Microwire* Frame Format
  316
  - FIFO Operation and Data Transfers
    317
    
    Using DMA Data Transfers
    317
    
    Using Programmed I/O Data Transfers
    317
  - Baud-Rate Generation
    317
  - SSP Serial Port Registers
    318
    
    SSP Control Register 0 (SSCR0)
    318
    
    SSCR0 Bit Definitions
    319
    
    SSCR1 Bit Definitions
    321
    
    SSP Control Register 1 (SSCR1)
    321
- Motorola SPI* Frame Formats for SPO and SPH Programming
  323
  - SSP Data Register (SSDR)
    325
- TFT and RFT Values for DMA Servicing
  325
  - SSDR Bit Definitions
    325
  - SSP Status Register (SSSR)
    326
  - SSSR Bit Definitions
    327
  - SSP Controller Register Summary
    329
100 C Bus Interface Unit

331
- Overview
  331
- Signal Description
  331
- Functional Description
  331
  - Operational Blocks
    333
  - I2C Bus Interface Modes
    333
- Modes of Operation
  333
  - Start and Stop Bus States
    334
- START and STOP Bit Definitions
  334
- Start and Stop Conditions
  335
  - START and STOP Conditions
    336
  - I2C Bus Operation
    337
    
    Data and Addressing Management
    337
    
    Serial Clock Line (SCL) Generation
    337
    
    I2C Acknowledge
    338
- Data Format of First Byte in Master Transaction
  338
  - Polling
    339
  - Arbitration
    339
- Clock Synchronization During the Arbitration Procedure
  340
  - Arbitration Procedure of Two Masters
    341
  - Master Operations
    342
- Master Transactions
  342
  - Slave Operations
    344
- Master-Receiver Read from Slave-Transmitter
  344
- Master-Receiver Read from Slave-Transmitter / Repeated Start / Master Transmitter Write to Slave-Receiver
  344
- A Complete Data Transfer
  344
- Slave Transactions
  345
  - General Call Address
    346
- Master-Transmitter Write to Slave-Receiver
  346
- Master-Receiver Read to Slave-Transmitter
  346
  - Master-Receiver Read to Slave-Transmitter, Repeated START, Master Transmitter Write to Slave-Receiver
    346
  - General Call Address Second Byte Definitions
    347
  - Slave Mode Programming Examples
    348
    
    Initialize Unit
    348
    
    Read N Bytes as a Slave
    348
    
    Write N Bytes as a Slave
    348
  - Master Programming Examples
    349
    
    Initialize Unit
    349
    
    Write 1 Byte as a Master
    349
    
    Read 1 Byte as a Master
    350
    
    Write 2 Bytes and Repeated Start Read 1 Byte as a Master
    350
    
    Read 2 Bytes as a Master - Send STOP Using the Abort
    351
  - Glitch Suppression Logic
    351
  - Reset Conditions
    351
  - Register Definitions
    352
- IBMR Bit Definitions
  352
  - I2C Control Register (ICR)
    353
- IDBR Bit Definitions
  353
- ICR Bit Definitions
  353
  - I2C Status Register (ISR)
    355
- ISR Bit Definitions
  356
- ISAR Bit Definitions
  357
10 Uarts

359
- Feature List
  359
- Overview
  360
  - Full Function UART
    360
  - Bluetooth UART
    360
  - Standard UART
    360
  - Compatibility with 16550
    360
- Signal Descriptions
  361
- UART Signal Descriptions
  361
- UART Operational Description
  362
- Example UART Data Frame
  362
  - Reset
    363
  - Internal Register Descriptions
    363
- Example NRZ Bit Encoding
  363
  - Receive Buffer Register (RBR)
    364
- UART Register Addresses as Offsets of a Base
  364
- RBR Bit Definitions
  364
- THR Bit Definitions
  365
- DLL Bit Definitions
  366
- DLH Bit Definitions
  366
- IER Bit Definitions
  367
- Interrupt Conditions
  368
- IIR Bit Definitions
  368
- Interrupt Identification Register Decode
  369
- FCR Bit Definitions
  370
- LCR Bit Definitions
  372
- LSR Bit Definitions
  373
- MCR Bit Definitions
  376
- MSR Bit Definitions
  378
  - FIFO Interrupt Mode Operation
    379
- SPR Bit Definitions
  379
  - FIFO Polled Mode Operation
    380
  - DMA Requests
    380
  - Slow Infrared Asynchronous Interface
    381
    
    ISR Bit Definitions
    382
    
    IR Transmit and Receive Example
    383
    
    XMODE Example
    383
  - UART Register Summary
    384
    
    BTUART Register Summary
    384
    
    FFUART Register Summary
    384
- STUART Register Summary
  385
  - UART Register Differences
    386
- Flow Control Registers in BTUART and STUART
  386
11 Fast Infrared Communication Port

387
- Signal Description
  387
- FICP Operation
  387
  - FICP Signal Description
    387
  - 4PPM Modulation
    388
  - PPM Modulation Encodings
    388
  - Address Field
    389
  - Control Field
    389
  - Data Field
    389
  - Frame Format
    389
  - Baud Rate Generation
    390
  - CRC Field
    390
  - Receive Operation
    390
  - Transmit Operation
    391
  - Transmit and Receive Fifos
    392
  - Trailing or Error Bytes in the Receive FIFO
    393
- FICP Register Definitions
  393
  - FICP Control Register 0 (ICCR0)
    394
- ICCR0 Bit Definitions
  394
  - FICP Control Register 1 (ICCR1)
    396
- ICCR1 Bit Definitions
  396
  - FICP Control Register 2 (ICCR2)
    397
- ICCR2 Bit Definitions
  397
  - FICP Data Register (ICDR)
    398
- ICRD Bit Definitions
  398
  - FICP Status Register 0 (ICSR0)
    399
- ICSR0 Bit Definitions
  399
  - FICP Status Register 1 (ICSR1)
    401
- ICSR1 Bit Definitions
  401
  - FICP Register Summary
    402

Intel PXA255 User Manual (198 pages)

XScale Microarchitecture

Brand: Intel | Category: Computer Hardware | Size: 2.86 MB

Table of Contents
3
1 Introduction

13
- About this Document
  13
  - How to Read this Document
    13
  - Other Relevant Documents
    13
- High-Level Overview of the Intel® Xscale™ Core as Implemented in the Application Processors
  14
  - ARM* Compatibility
    14
  - Features
    15
    
    Memory Management
    15
    
    Multiply/Accumulate (MAC)
    15
- Intel® Xscale™ Microarchitecture Architecture Features
  15
  - Instruction Cache
    16
  - Branch Target Buffer
    16
  - Data Cache
    16
  - Fill Buffer & Write Buffer
    16
  - Memory Management
    16
  - Performance Monitoring
    17
  - Power Management
    17
  - Debug
    17
- Terminology and Conventions
  17
  - Number Representation
    17
  - Terminology and Acronyms
    18
2 Programming Model

19
- ARM* Architecture Compatibility
  19
- ARM* Architecture Implementation Options
  19
  - Big Endian Versus Little Endian
    19
  - Thumb
    19
  - ARM* DSP-Enhanced Instruction Set
    20
  - Base Register Update
    20
- Extensions to ARM* Architecture
  20
  - DSP Coprocessor 0 (CP0)
    21
    
    Multiply with Internal Accumulate Format
    21
    
    Multiply with Internal Accumulate Format
    22
    
    Miaph{<Cond>} Acc0, Rm, Rs
    23
    
    Internal Accumulator Access Format
    24
    
    Internal Accumulator Access Format
    25
    
    Mar{<Cond>} Acc0, Rdlo, Rdhi
    26
  - New
    27
  - Additions to CP15 Functionality
    28
  - Event Architecture
    29
    
    Event Priority
    29
    
    Exception Summary
    29
    
    Data Aborts
    30
    
    Prefetch Aborts
    30
    
    Intel® Xscale™ Core Encoding of Fault Status for Data Aborts
    31
    
    Events from Preload Instructions
    32
    
    Debug Events
    33
3 Memory Management

35
- Overview
  35
- Architecture Model
  35
  - Version 4 Vs. Version 5
    36
  - Instruction Cache
    36
  - Data Cache and Write Buffer
    36
  - Details on Data Cache and Write Buffer Behavior
    37
  - Memory Operation Ordering
    37
  - Exceptions
    38
- Interaction of the MMU, Instruction Cache, and Data Cache
  38
- Control
  38
  - Invalidate (Flush) Operation
    38
  - Enabling/Disabling
    39
  - Locking Entries
    39
  - Round-Robin Replacement Algorithm
    41
- Example of Locked Entries in TLB
  42
4 Instruction Cache

43
- Overview
  43
- Instruction Cache Organization
  43
- Operation
  44
  - Instruction Cache Is Enabled
    44
  - The Instruction Cache Is Disabled
    44
  - Fetch Policy
    44
  - Round-Robin Replacement Algorithm
    45
  - Parity Protection
    45
  - Instruction Fetch Latency
    46
  - Instruction Cache Coherency
    46
- Instruction Cache Control
  47
- Locked Line Effect on Round Robin Replacement
  48
  - Unlocking Instructions in the Instruction Cache
    49
5 Branch Target Buffer

51
- Branch Target Buffer (BTB) Operation
  51
  - Reset
    52
  - Update Policy
    52
- BTB Control
  52
  - Disabling/Enabling
    52
  - Invalidation
    53
6 Data Cache

55
- Overviews
  55
- Data Cache and Mini-Data Cache Operation
  58
  - Operation When Caching Is Enabled
    58
  - Operation When Data Caching Is Disabled
    58
  - Cache Policies
    58
    
    Cacheability
    58
    
    Read Miss Policy
    58
    
    Write Miss Policy
    59
    
    Write-Back Versus Write-Through
    60
  - Round-Robin Replacement Algorithm
    60
  - Parity Protection
    60
  - Atomic Accesses
    61
- Data Cache and Mini-Data Cache Control
  61
- Re-Configuring the Data Cache as Data RAM
  64
- Write Buffer/Fill Buffer Operation and Control
  67
7 Configuration

69
8 Performance Monitoring

87
9 Test

97
- Boundary-Scan Architecture and Overview
  97
- Reset
  98
- Instruction Register
  99
  - Boundary-Scan Instruction Set
    99
- JTAG Instruction Descriptions
  100
  - Test Data Registers
    101
    
    Boundary-Scan Register
    101
    
    Bypass Register
    101
    
    Device Identification (ID) Code Register
    103
    
    Data Specific Registers
    104
  - TAP Controller
    104
    
    Run-Test/Idle State
    105
    
    Test Logic Reset State
    105
    
    Capture-DR State
    106
    
    Exit1-DR State
    106
    
    Select-DR-Scan State
    106
    
    Shift-DR State
    106
    
    Capture-IR State
    107
    
    Exit2-DR State
    107
    
    Pause-DR State
    107
    
    Select-IR Scan State
    107
    
    Update-DR State
    107
    
    Exit1-IR State
    108
    
    Exit2-IR State
    108
    
    Pause-IR State
    108
    
    Shift-IR State
    108
    
    Update-IR State
    108
10 Software Debug

111
- Introduction
  111
  - Halt Mode
    111
  - Monitor Mode
    112
- Debug Registers
  112
- Debug Control and Status Register (DCSR)
  113
  - Global Enable Bit (GE)
    114
  - Halt Mode Bit (H)
    114
  - Vector Trap Bits (TF,TI,TD,TA,TS,TU,TR)
    114
  - Sticky Abort Bit (SA)
    115
  - Method of Entry Bits (MOE)
    115
  - Trace Buffer Mode Bit (M)
    115
  - Trace Buffer Enable Bit (E)
    115
- Debug Exceptions
  115
  - Halt Mode
    116
  - Monitor Mode
    117
- HW Breakpoint Resources
  118
  - Instruction Breakpoints
    119
  - Data Breakpoints
    119
- Data Breakpoint Controls Register (DBCON)
  120
  - Software Breakpoints
    121
  - Transmit/Receive Control Register (TXRXCTRL)
    121
    
    RX Register Ready Bit (RR)
    122
    
    Download Flag (D)
    123
    
    Overflow Flag (OV)
    123
    
    Conditional Execution Using TXRXCTRL
    124
    
    TX Register Ready Bit (TR)
    124
  - Transmit Register (TX)
    125
  - Receive Register (RX)
    125
  - Debug JTAG Access
    126
    
    SELDCSR JTAG Command
    126
    
    SELDCSR JTAG Register
    127
    
    Dbg.brk
    128
    
    Dbg.dcsr
    128
    
    Dbg.hld_Rst
    128
    
    DBGTX JTAG Command
    129
    
    DBGTX JTAG Register
    129
    
    DBGRX JTAG Command
    130
    
    DBGRX JTAG Register
    130
    
    DBGRX Data Register
    131
    
    RX Write Logic
    131
    
    Dbg.rr
    132
    
    Dbg.rx
    132
    
    Dbg.V
    132
    
    Dbg.D
    133
    
    Dbg.flush
    133
    
    Debug JTAG Data Register Reset Values
    133
  - Trace Buffer
    133
    
    Trace Buffer CP Registers
    133
    
    Checkpoint Registers
    134
    
    Trace Buffer Register (TBREG)
    135
    
    Trace Buffer Usage
    135
- High Level View of Trace Buffer
  136
  - Trace Buffer Entries
    137
    
    Message Byte
    137
    
    Exception Message Byte
    138
    
    Non-Exception Message Byte
    138
    
    Address Bytes
    139
  - Downloading Code into the Instruction Cache
    140
    
    LDIC JTAG Command
    140
    
    LDIC JTAG Data Register
    141
    
    LDIC Cache Functions
    142
    
    Loading IC During Reset
    143
    
    Loading IC During Cold Reset for Debug
    144
- Code Download During a Cold Reset for Debug
  145
  - Loading IC During a Warm Reset for Debug
    146
- Code Download During a Warm Reset for Debug
  147
  - Dynamically Loading IC after Reset
    148
    
    Dynamic Code Download Synchronization
    149
    
    Mini Instruction Cache Overview
    150
  - Halt Mode Software Protocol
    150
    
    Starting a Debug Session
    150
    
    Placing the Handler in Memory
    151
    
    Setting up Override Vector Tables
    151
    
    Debug Handler Entry
    152
    
    Debug Handler Restrictions
    152
    
    Implementing a Debug Handler
    152
    
    Dynamic Debug Handler
    153
    
    High-Speed Download
    154
    
    Ending a Debug Session
    155
  - Software Debug Notes
    156

Intel PXA255 Datasheet (40 pages)

Electrical, Mechanical, and Thermal Specification

Brand: Intel | Category: Computer Hardware | Size: 1.18 MB

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Intel PXA255 Manuals

Intel PXA255 Developer's Manual (600 pages)

Table of Contents

1 Introduction

2 System Architecture

3 Clocks and Power Manager

4 System Integration Unit

5 DMA Controller

6 Memory Controller

7 LCD Controller

8 Synchronous Serial Port Controller

100 C Bus Interface Unit

10 Uarts

11 Fast Infrared Communication Port

Intel PXA255 User Manual (198 pages)

Table of Contents

1 Introduction

2 Programming Model

3 Memory Management

4 Instruction Cache

5 Branch Target Buffer

6 Data Cache

7 Configuration

8 Performance Monitoring

9 Test

10 Software Debug

Intel PXA255 Datasheet (40 pages)

Table of Contents

About this Document

Functional Overview

Package Information

Electrical Specifications

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