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Intel Pentium II Manuals
Manuals and User Guides for Intel Pentium II. We have
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Intel Pentium II manuals available for free PDF download: Developer's Manual, Application Note
Intel Pentium II Developer's Manual (226 pages)
Brand:
Intel
| Category:
Computer Hardware
| Size: 2.47 MB
Table of Contents
3
Table of Contents
11
Chapter 1
11
Component Introduction
13
System Overview
14
Terminology
15
Cartridge Terminology
15
References
17
Chapter 2
17
Micro-Architecture Overview
19
Appendix A
19
Three Engines Communicating Using an Instruction Pool
20
Full Core Utilization
21
The Pentium ® II Processor Pipeline
22
The Fetch/Decode Unit
23
The Dispatch/Execute Unit
24
The Retire Unit
25
The Bus Interface Unit
26
Inside the Bus Interface Unit
27
MMX™ Technology and the Pentium ® II Processor
28
Out of Order Core and Retirement Pipeline
30
Additional Information
31
Caches
32
Write Buffers
32
Additional Information
32
Architecture Summary
19
Chapter 14
33
Chapter 3
33
System Bus Overview
35
Latched Bus Protocol
36
Signal Overview
36
Execution Control Signals
37
Arbitration Signals
38
Arbitration Signals
39
Request Signals
39
Snoop Signals
40
Response Signals
41
Data Response Signals
41
Error Signals
43
Compatibility Signals
44
Diagnostic Signals
45
Chapter 4
45
Data Integrity
47
Error Classification
48
Bus Signals Protected Directly
49
Bus Signals Protected Indirectly
49
Unprotected Bus Signals
50
Hard-Error Response
50
Parity Algorithm
53
Chapter 5
53
Description
54
Output Tristate
54
Built-In Self Test
55
Data Bus Error Checking Policy
55
Response Signal Parity Error Checking Policy
55
AERR# Driving Policy
55
AERR# Observation Policy
55
BERR# Driving Policy for Initiator Bus Errors
55
BERR# Driving Policy for Target Bus Errors
56
Bus Error Driving Policy for Initiator Internal Errors
56
BINIT# Driving Policy
56
BINIT# Observation Policy
56
In-Order Queue Pipelining
56
Power-On Reset Vector
56
FRC Mode Enable
57
APIC Mode
57
APIC Cluster ID
57
Symmetric Agent Arbitration ID
58
Low Power Standby Enable
58
Clock Frequencies and Ratios
59
Software-Programmable Options
61
Initialization Process
63
Chapter 6
63
Test Access Port (Tap)
65
Interface
66
Accessing the Tap Logic
67
TAP Controller Finite State Machine
68
Accessing the Instruction Register
69
Processor TAP Instruction Register
70
Accessing the Data Registers
71
Instruction Set
72
Data Register Summary
72
Bypass Register
72
Device ID Register
73
BIST Result Boundary Scan Register
73
Boundary Scan Register
73
Reset Behavior
75
Chapter 7
75
Electrical Specifications
77
GTL+ Bus Topology
78
Clock Control and Low Power States
80
Halt/Grant Snoop State — State 4
81
Normal State - State 1
81
Deep Sleep State - 6
81
Clock Control and Low Power Modes
81
Power and Ground Pins
82
Decoupling Guidelines
82
System Bus GTL+ Decoupling
83
System Bus Clock and Processor Clocking
84
Example Schematic for Clock Ratio Pin Sharing
85
Mixing Processors of Different Frequencies
85
Voltage Identification
88
Asynchronous Vs. Synchronous for System Bus Signals
88
Pentium ® II Processor System Bus Signal Groups
90
Test Access Port (Tap) Connection
90
Maximum Ratings
90
Processor System Bus DC Specifications
94
GTL+ Signal Groups DC Specifications
98
System Bus AC Specifications (Reset Conditions)
101
BCLK to Core Logic Offset
102
System Bus Valid Delay Timings
103
FRC Mode BCLK to PICCLK Timing
104
Power-On Reset and Configuration Timings
105
Test Timings (TAP Connection)
107
Chapter 8
107
Gtl+ Interface Specifications
109
System Specification
110
System Bus Specifications
111
System AC Parameters: Signal Quality
112
Specifications for Signal Quality
113
Ringback Tolerance
115
AC Parameters: Flight Time
116
Measuring Nominal Flight Time
117
Flight Time of a Rising Edge Slower Than 0.3V/Ns
118
Extrapolated Flight Time of a Non-Monotonic Rising Edge
119
Extrapolated Flight Time of a Non-Monotonic Falling Edge
121
General Gtl+ I/O Buffer Specification
121
I/O Buffer DC Specification
122
I/O Buffer AC Specifications
122
Determining Clock-To-Out, Setup and Hold
122
Clock-To-Output Time, Tco
123
Test Load for Measuring Output AC Timings
124
Minimum Setup and Hold Times
125
Standard Input Lo-To-Hi Waveform for Characterizing Receiver Setup Time
126
Standard Input Hi-To-Lo Waveform for Characterizing Receiver Setup Time
127
Receiver Ringback Tolerance
127
System-Based Calculation of Required Input and Output Timings
127
Calculating Target T Flight_Max
128
Calculating Target Thold
128
Package Specification
129
Chapter 9
129
Signal Quality Specifications
131
System Bus Clock (Bclk) Signal Quality Specifications
132
BCLK, TCK PICCLK Generic Clock Waveform at the Processor Edge Fingers
133
Gtl+ Signal Quality Specifications
133
Non-Gtl+ Signal Quality Specifications
133
Overshoot/Undershoot Guidelines
134
Ringback Specification
135
Settling Limit Guideline
137
Chapter 10
137
Thermal Specifications and Design Considerations
139
Thermal Specifications
139
Processor S.E.C. Cartridge Thermal Plate
140
Thermal Solution Performance
141
Measurements for Thermal Specifications
141
Thermal Plate Temperature Measurement
142
Processor Thermal Plate Temperature Measurement Location
143
Cover Temperature Measurement
144
Thermal Solution Attach Methods
145
Heatsink Clip Attach
146
Processor with an Example Low Profile Heatsink Attached Using Spring Clips
147
Rivscrew* Attach
148
General Rivscrew* Heatsink Mechanical Recommendations
149
Chapter 11
149
Cartridge Mechanical Specifications
151
Cartridge Materials Information
152
S.E.C. Cartridge Materials
153
S.E.C. Cartridge—Thermal Plate and Cover Side Views
154
S.E.C. Cartridge Top and Side Views
155
S.E.C. Cartridge Bottom Side View
156
S.E.C. Cartridge Thermal Plate Side Dimensions
157
S.E.C. Cartridge Thermal Plate Attachment Detail Dimensions
158
S.E.C. Cartridge Latch Arm, Thermal Plate Lug and Cover Lug Dimensions
159
S.E.C. Cartridge Latch Arm, Cover and Thermal Plate Detail Dimensions
160
S.E.C. Cartridge Substrate Dimensions (Skirt Not Shown for Clarity)
161
S.E.C. Cartridge Substrate—Detail a
162
S.E.C. Cartridge Mark Locations (Processor Markings)
163
Processor Edge Finger Signal Listing
168
Signal Listing in Order By Signal Name
173
Chapter 12
173
Boxed Processor Specifications
175
Introduction
176
Mechanical Specifications
176
Boxed Processor Fan/Heatsink Dimensions
177
Side View Space Requirements for the Boxed Processor (Fan/Heatsink Supports Not Shown)
178
Boxed Processor Fan/Heatsink Weight
178
Boxed Processor Retention Mechanism and Fan/Heatsink Support
179
Boxed Processor Fan/Heatsink Support Dimensions
180
Heatsink Support Hole Locations and Sizes
181
Side View Space Requirements for Boxed Processor Fan/Heatsink Supports
182
Boxed Processor Requirements
182
Fan/Heatsink Power Supply
183
Boxed Processor Fan/Heatsink Power Cable Connector Description
184
Thermal Specifications
184
Boxed Processor Cooling Requirements
185
Chapter 13
185
Integration Tools
187
Primary Function
187
In-Target Probe (Itp) for the Pentium ® II Processor
188
Debug Port Connector Description
188
Debug Port Signal Descriptions
189
Debug Port Signal Notes
189
Signal Note 1: Dbreset
189
Signal Note 5: Tdo and Tdi
190
Debug Port Pinout Description and Requirements 1
193
Signal Note 7: Tck
194
Debug Port Layout
195
Generic DP System Layout for Debug Port Connection
196
Signal Quality Notes
196
Debug Port Connector
197
Using Boundary Scan to Communicate to the Processor
197
Integration Tool Considerations
197
Integration Tool Mechanical Keepouts
198
LAI Probe Input Circuit
199
Pentium ® II Processor Integration Tool Mechanical Keep Out Volume Thermal Plate Side View
201
Side View
212
A-1. BR0#(I/O), BR1#, BR2#, BR3# Signals Rotating Interconnect
219
A-1. PWRGOOD Relationship at Power-On
221
A-4. Slot 1 Occupation Truth Table
226
A-7. Input/Output Signals (Single Driver)
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Intel Pentium II Application Note (16 pages)
Brand:
Intel
| Category:
Computer Hardware
| Size: 0.14 MB
Table of Contents
1
Pentium II Processor
3
Table of Contents
5
Introduction
5
Key Terms
5
Related Documents
5
Related Intel Documents
6
Simulation Prerequisites
6
Simulation Block Diagram
7
Details of the Electrical Interconnect Models
7
Simulation Model Components
7
Fast, Slow, and Worst-Case Signal Quality Corner Interconnect Models
8
Simulation Conditions
8
400-Pin Connector Package Model
8
DIMM Connector Package Model
9
DIMM Connection
9
Low-Power Module Memory Interface Pin Loading
10
Simulation Conditions
11
Flight Time and Signal Quality Definitions
11
Procedure 1: Determining Flight Time
11
Determining Flight Time
12
Flight Time Determination for Setup Time
12
Flight Time (Rising Edge)
13
Hold Time
13
Flight Time (Falling Edge)
14
Procedure 2: Signal Quality
14
Signal Quality Criteria
15
Flight Time Measurement (With Ringing)
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