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Intel Pentium II Manuals
Manuals and User Guides for Intel Pentium II. We have
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Intel Pentium II manuals available for free PDF download: Developer's Manual, Application Note
Intel Pentium II Developer's Manual (226 pages)
Brand:
Intel
| Category:
Computer Hardware
| Size: 2 MB
Table of Contents
Table of Contents
3
Chapter 1 Component Introduction
11
System Overview
13
Terminology
14
Cartridge Terminology
15
References
15
Chapter 2 Micro-Architecture Overview
17
Chapter 14 Advanced Features 14.1. Additional Information ................................................................................14-1 Appendix A
19
Three Engines Communicating Using an Instruction Pool
19
Full Core Utilization
20
The Pentium ® II Processor Pipeline
21
The Fetch/Decode Unit
22
The Dispatch/Execute Unit
23
The Retire Unit
24
The Bus Interface Unit
25
Inside the Bus Interface Unit
26
MMX™ Technology and the Pentium ® II Processor
27
Out of Order Core and Retirement Pipeline
28
Additional Information
30
Caches
31
Write Buffers
32
Additional Information
32
Architecture Summary
32
Chapter 3 System Bus Overview
33
Latched Bus Protocol
35
Signal Overview
36
Execution Control Signals
36
Arbitration Signals
37
Arbitration Signals
38
Request Signals
39
Snoop Signals
39
Response Signals
40
Data Response Signals
41
Error Signals
41
Compatibility Signals
43
Diagnostic Signals
44
Chapter 4 Data Integrity
45
Error Classification
47
Bus Signals Protected Directly
48
Bus Signals Protected Indirectly
49
Unprotected Bus Signals
49
Hard-Error Response
50
Parity Algorithm
50
Chapter 5 Configuration
53
Description
53
Output Tristate
54
Built-In Self Test
54
Data Bus Error Checking Policy
55
Response Signal Parity Error Checking Policy
55
AERR# Driving Policy
55
AERR# Observation Policy
55
BERR# Driving Policy for Initiator Bus Errors
55
BERR# Driving Policy for Target Bus Errors
55
Bus Error Driving Policy for Initiator Internal Errors
56
BINIT# Driving Policy
56
BINIT# Observation Policy
56
In-Order Queue Pipelining
56
Power-On Reset Vector
56
FRC Mode Enable
56
APIC Mode
57
APIC Cluster ID
57
Symmetric Agent Arbitration ID
57
Low Power Standby Enable
58
Clock Frequencies and Ratios
58
Software-Programmable Options
59
Initialization Process
61
Chapter 6 Test Access Port (Tap)
63
Interface
65
Accessing the Tap Logic
66
TAP Controller Finite State Machine
67
Accessing the Instruction Register
68
Processor TAP Instruction Register
69
Accessing the Data Registers
70
Instruction Set
71
Data Register Summary
72
Bypass Register
72
Device ID Register
72
BIST Result Boundary Scan Register
73
Boundary Scan Register
73
Reset Behavior
73
Chapter 7 Electrical Specifications
75
GTL+ Bus Topology
77
Clock Control and Low Power States
78
Halt/Grant Snoop State — State 4
80
Normal State - State 1
81
Deep Sleep State - 6
81
Clock Control and Low Power Modes
81
Power and Ground Pins
81
Decoupling Guidelines
82
System Bus GTL+ Decoupling
82
System Bus Clock and Processor Clocking
83
Example Schematic for Clock Ratio Pin Sharing
84
Mixing Processors of Different Frequencies
85
Voltage Identification
85
Asynchronous Vs. Synchronous for System Bus Signals
88
Pentium ® II Processor System Bus Signal Groups
88
Test Access Port (Tap) Connection
90
Maximum Ratings
90
Processor System Bus DC Specifications
90
GTL+ Signal Groups DC Specifications
94
System Bus AC Specifications (Reset Conditions)
98
BCLK to Core Logic Offset
101
System Bus Valid Delay Timings
102
FRC Mode BCLK to PICCLK Timing
103
Power-On Reset and Configuration Timings
104
Test Timings (TAP Connection)
105
Chapter 8 Gtl+ Interface Specifications
107
System Specification
109
System Bus Specifications
110
System AC Parameters: Signal Quality
111
Specifications for Signal Quality
112
Ringback Tolerance
113
AC Parameters: Flight Time
115
Measuring Nominal Flight Time
116
Flight Time of a Rising Edge Slower than 0.3V/Ns
117
Extrapolated Flight Time of a Non-Monotonic Rising Edge
118
Extrapolated Flight Time of a Non-Monotonic Falling Edge
119
General Gtl+ I/O Buffer Specification
121
I/O Buffer DC Specification
121
I/O Buffer AC Specifications
122
Determining Clock-To-Out, Setup and Hold
122
Clock-To-Output Time, Tco
122
Test Load for Measuring Output AC Timings
123
Minimum Setup and Hold Times
124
Standard Input Lo-To-Hi Waveform for Characterizing Receiver Setup Time
125
Standard Input Hi-To-Lo Waveform for Characterizing Receiver Setup Time
126
Receiver Ringback Tolerance
127
System-Based Calculation of Required Input and Output Timings
127
Calculating Target T Flight_Max
127
Calculating Target Thold
128
Package Specification
128
Chapter 9 Signal Quality Specifications
129
System Bus Clock (Bclk) Signal Quality Specifications
131
BCLK, TCK PICCLK Generic Clock Waveform at the Processor Edge Fingers
132
Gtl+ Signal Quality Specifications
133
Non-Gtl+ Signal Quality Specifications
133
Overshoot/Undershoot Guidelines
133
Ringback Specification
134
Settling Limit Guideline
135
Chapter 10 Thermal Specifications and Design Considerations
137
Thermal Specifications
139
Processor S.E.C. Cartridge Thermal Plate
139
Thermal Solution Performance
140
Measurements for Thermal Specifications
141
Thermal Plate Temperature Measurement
141
Processor Thermal Plate Temperature Measurement Location
142
Cover Temperature Measurement
143
Thermal Solution Attach Methods
144
Heatsink Clip Attach
145
Processor with an Example Low Profile Heatsink Attached Using Spring Clips
146
Rivscrew* Attach
147
General Rivscrew* Heatsink Mechanical Recommendations
148
Chapter 11 Cartridge Mechanical Specifications
149
Cartridge Materials Information
151
S.E.C. Cartridge Materials
152
S.E.C. Cartridge—Thermal Plate and Cover Side Views
153
S.E.C. Cartridge Top and Side Views
154
S.E.C. Cartridge Bottom Side View
155
S.E.C. Cartridge Thermal Plate Side Dimensions
156
S.E.C. Cartridge Thermal Plate Attachment Detail Dimensions
157
S.E.C. Cartridge Latch Arm, Thermal Plate Lug and Cover Lug Dimensions
158
S.E.C. Cartridge Latch Arm, Cover and Thermal Plate Detail Dimensions
159
S.E.C. Cartridge Substrate Dimensions (Skirt Not Shown for Clarity)
160
S.E.C. Cartridge Substrate—Detail a
161
S.E.C. Cartridge Mark Locations (Processor Markings)
162
Processor Edge Finger Signal Listing
163
Signal Listing in Order by Signal Name
168
Chapter 12 Boxed Processor Specifications
173
Introduction
175
Mechanical Specifications
176
Boxed Processor Fan/Heatsink Dimensions
176
Side View Space Requirements for the Boxed Processor (Fan/Heatsink Supports Not Shown)
177
Boxed Processor Fan/Heatsink Weight
178
Boxed Processor Retention Mechanism and Fan/Heatsink Support
178
Boxed Processor Fan/Heatsink Support Dimensions
179
Heatsink Support Hole Locations and Sizes
180
Side View Space Requirements for Boxed Processor Fan/Heatsink Supports
181
Boxed Processor Requirements
182
Fan/Heatsink Power Supply
182
Boxed Processor Fan/Heatsink Power Cable Connector Description
183
Thermal Specifications
184
Boxed Processor Cooling Requirements
184
Chapter 13 Integration Tools
185
Primary Function
187
In-Target Probe (Itp) for the Pentium ® II Processor
187
Debug Port Connector Description
188
Debug Port Signal Descriptions
188
Debug Port Signal Notes
189
Signal Note 1: Dbreset
189
Signal Note 5: Tdo and Tdi
189
Debug Port Pinout Description and Requirements 1
190
Signal Note 7: Tck
193
Debug Port Layout
194
Generic DP System Layout for Debug Port Connection
195
Signal Quality Notes
196
Debug Port Connector
196
Using Boundary Scan to Communicate to the Processor
197
Integration Tool Considerations
197
Integration Tool Mechanical Keepouts
197
LAI Probe Input Circuit
198
Pentium ® II Processor Integration Tool Mechanical Keep out Volume Thermal Plate Side View
199
Side View
201
A-1. BR0#(I/O), BR1#, BR2#, BR3# Signals Rotating Interconnect
212
A-1. PWRGOOD Relationship at Power-On
219
A-4. Slot 1 Occupation Truth Table
221
A-7. Input/Output Signals (Single Driver)
226
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Intel Pentium II Application Note (16 pages)
Brand:
Intel
| Category:
Computer Hardware
| Size: 0 MB
Table of Contents
Pentium II Processor
1
Table of Contents
3
Introduction
5
Key Terms
5
Related Documents
5
Related Intel Documents
5
Simulation Prerequisites
6
Simulation Block Diagram
6
Details of the Electrical Interconnect Models
7
Simulation Model Components
7
Fast, Slow, and Worst-Case Signal Quality Corner Interconnect Models
7
Simulation Conditions
8
400-Pin Connector Package Model
8
DIMM Connector Package Model
8
DIMM Connection
9
Low-Power Module Memory Interface Pin Loading
9
Simulation Conditions
10
Flight Time and Signal Quality Definitions
11
Procedure 1: Determining Flight Time
11
Determining Flight Time
11
Flight Time Determination for Setup Time
12
Flight Time (Rising Edge)
12
Hold Time
13
Flight Time (Falling Edge)
13
Procedure 2: Signal Quality
14
Signal Quality Criteria
14
Flight Time Measurement (with Ringing)
15
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