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i960

Jx Microprocessor

Developer's Manual

Release Date: December, 1997

Order Number: 272483-002

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Summary of Contents for Intel i960 Jx

Page 1 ® i960 Jx Microprocessor Developer’s Manual Release Date: December, 1997 Order Number: 272483-002...
Page 2 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
Page 3: Table Of Contents
® i960 Jx Microprocessor Developer’s Manual CHAPTER 1 INTRODUCTION Product Features......................1-4 1.1.1 Instruction Cache ....................1-4 1.1.2 Data Cache ......................1-4 1.1.3 On-chip (Internal) Data RAM ................... 1-4 1.1.4 Local Register Cache ....................1-5 1.1.5 Interrupt Controller ....................1-5 1.1.6 Timer Support ......................
Page 4 CHAPTER 3 PROGRAMMING ENVIRONMENT OVERVIEW ........................3-1 REGISTERS AND LITERALS AS INSTRUCTION OPERANDS........3-1 3.2.1 Global Registers ...................... 3-2 3.2.2 Local Registers ......................3-3 3.2.3 Register Scoreboarding ................... 3-4 3.2.4 Literals ........................3-4 3.2.5 Register and Literal Addressing and Alignment ............3-4 MEMORY-MAPPED CONTROL REGISTERS..............
Page 5 4.4.4 Instruction Cache Visibility ..................4-5 4.4.5 Instruction Cache Coherency .................. 4-5 DATA CACHE ....................... 4-6 4.5.1 Enabling and Disabling the Data Cache ..............4-6 4.5.2 Multi-Word Data Accesses that Partially Hit the Data Cache ........4-7 4.5.3 Data Cache Fill Policy ..................... 4-8 4.5.4 Data Cache Write Policy ..................
Page 6 5.2.12 Processor Management ..................5-19 PERFORMANCE OPTIMIZATION ................5-20 5.3.1 Instruction Optimizations ..................5-20 5.3.1.1 Load / Store Execution Model ................ 5-20 5.3.1.2 Compare Operations ..................5-20 5.3.1.3 Microcoded Instructions ................. 5-21 5.3.1.4 Multiply-Divide Unit Instructions ..............5-21 5.3.1.5 Multi-Cycle Register Operations ..............5-21 5.3.1.6 Simple Control Transfer .................
Page 7 6.2.14 calls ........................6-25 6.2.15 callx ........................6-27 6.2.16 chkbit ........................6-29 6.2.17 clrbit ........................6-30 6.2.18 cmpdeci, cmpdeco ....................6-31 6.2.19 cmpinci, cmpinco ....................6-32 6.2.20 COMPARE ......................6-33 6.2.21 COMPARE AND BRANCH<cc> ................6-35 6.2.22 concmpi, concmpo ....................6-38 6.2.23 dcctl ........................
Page 8 6.2.58 SEL<cc> ........................ 6-97 6.2.59 setbit ........................6-99 6.2.60 SHIFT ........................6-100 6.2.61 spanbit ......................... 6-103 6.2.62 STORE ........................ 6-104 6.2.63 subc ........................6-108 6.2.64 SUB<cc> ......................6-109 6.2.65 subi, subo ......................6-112 6.2.66 syncf ........................6-113 6.2.67 sysctl ........................6-114 6.2.68 TEST<cc>...
Page 9 BRANCH-AND-LINK ....................7-21 CHAPTER 8 FAULTS FAULT HANDLING OVERVIEW ................... 8-1 FAULT TYPES ......................8-3 FAULT TABLE ......................8-4 STACK USED IN FAULT HANDLING................8-6 FAULT RECORD ......................8-6 8.5.1 Fault Record Description ..................8-7 8.5.2 Fault Record Location ..................... 8-8 MULTIPLE AND PARALLEL FAULTS ................
Page 10 8.10.3 OPERATION Faults ....................8-24 8.10.4 OVERRIDE Faults ....................8-26 8.10.5 PARALLEL Faults ....................8-27 8.10.6 PROTECTION Faults .................... 8-28 8.10.7 TRACE Faults ......................8-29 8.10.8 TYPE Faults ......................8-32 CHAPTER 9 TRACING AND DEBUGGING TRACE CONTROLS ..................... 9-1 9.1.1 Trace Controls (TC) Register ...................
Page 11 10.1.1.5 Bits 4, 5 - Timer Input Clock Select (TMRx.csel1:0) ........10-6 10.1.2 Timer Count Register (TCR0, TCR1) ..............10-6 10.1.3 Timer Reload Register (TRR0, TRR1) ..............10-7 10.2 TIMER OPERATION ....................10-7 10.2.1 Basic Timer Operation ................... 10-7 10.2.2 Load/Store Access Latency for Timer Registers ...........
Page 12 11.7.5 Interrupt Mapping Registers (IMAP0-IMAP2) ............11-23 11.7.5.1 Interrupt Mask (IMSK) and Interrupt Pending (IPND) Registers ....11-25 11.7.5.2 Interrupt Controller Register Access Requirements ........11-27 11.7.5.3 Default and Reset Register Values .............. 11-28 11.8 INTERRUPT OPERATION SEQUENCE..............11-28 11.8.1 Setting Up the Interrupt Controller ...............
Page 13 12.6 SYSTEM REQUIREMENTS..................12-34 12.6.1 Input Clock (CLKIN) .................... 12-34 12.6.2 Power and Ground Requirements (V ) ............. 12-34 12.6.3 Pin Requirements ..................12-35 12.6.4 Power and Ground Planes .................. 12-35 12.6.5 Decoupling Capacitors ..................12-36 12.6.6 I/O Pin Characteristics ..................12-36 12.6.6.1 Output Pins ....................
Page 14 14.2 BUS OPERATION ....................... 14-1 14.2.1 Basic Bus States ....................14-2 14.2.2 Bus Signal Types ....................14-4 14.2.2.1 Clock Signal ....................14-4 14.2.2.2 Address/Data Signal Definitions ..............14-4 14.2.2.3 Control/Status Signal Definitions ..............14-4 14.2.3 Bus Accesses ......................14-6 14.2.3.1 Bus Width .......................
Page 15 Implementation-Specific Instructions ................. A-5 EXTENDED REGISTER SET................... A-5 INITIALIZATION ....................... A-5 MEMORY CONFIGURATION ..................A-6 INTERRUPTS ........................A-6 A.10 OTHER i960 Jx PROCESSOR IMPLEMENTATION-SPECIFIC FEATURES....A-6 A.10.1 Data Control Peripheral Units ..................A-7 A.10.2 Timers ........................A-7 A.10.3 Fault Implementation ....................A-7 A.11...
Page 16 APPENDIX C MACHINE-LEVEL INSTRUCTION FORMATS GENERAL INSTRUCTION FORMAT................C-1 REG FORMAT......................... C-2 COBR FORMAT ......................C-3 CTRL FORMAT ....................... C-4 MEM FORMAT ........................ C-4 C.5.1 MEMA Format Addressing ..................C-5 C.5.2 MEMB Format Addressing ..................C-6 APPENDIX D REGISTER AND DATA STRUCTURES REGISTERS ........................
Page 17 FIGURES ® Figure 1-1. i960 Jx Microprocessor Functional Block Diagram..........1-3 Figure 2-1. Data Types and Ranges ..................2-1 Figure 2-2. Data Placement in Registers ................2-6 ® Figure 3-1. i960 Jx Processor Programming Environment Elements ........3-2 Figure 3-2. Memory Address Space ..................
Page 18 Figure 11-5. Expanded Mode ....................11-15 Figure 11-6. Implementation of Expanded Mode Sources........... 11-16 Figure 11-7. Interrupt Sampling ................... 11-20 Figure 11-8. Interrupt Control (ICON) Register..............11-22 Figure 11-9. Interrupt Mapping (IMAP0-IMAP2) Registers ..........11-24 Figure 11-10. Interrupt Pending (IPND) Register..............11-25 Figure 11-11.
Page 19 Figure 14-12. Burst Read/Write Transactions with 1,0 Wait States, Extra Tr State on Read, 16-Bit Bus 14-21 Figure 14-13. Summary of Aligned and Unaligned Accesses (32-Bit Bus) ......14-25 Figure 14-14. Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) ..14-26 Figure 14-15.
Page 20 Figure D-23. Control Table ..................... D-22 Figure D-24. IEEE 1149.1 Device Identification Register............D-23 Figure D-25. PMCON Register Bit Description............... D-23 Figure D-26. BCON (Bus Control) Register................D-24 Figure D-27. DLMCON (Default Logical Memory Configuration) Register ......D-24 Figure D-28. LMADR0:1 Logical Memory Template Starting Address Registers ....
Page 21 TABLES Table 1-1. Register Terminology Conventions ..............1-10 Table 2-1. Memory Contents for Little and Big Endian Example .......... 2-5 Table 2-2. Byte Ordering for Little and Big Endian Accesses ..........2-5 Table 2-3. Memory Addressing Modes ................. 2-6 Table 3-1. Registers and Literals Used as Instruction Operands .........
Page 22 PMCON Address Mapping ................13-4 Table 13-2. DLMCON Values at Reset ................13-13 Table 14-1. Summary of i960 Jx Processor Bus Signals ............14-5 Table 14-2. 8-Bit Bus Width Byte Enable Encodings............14-8 Table 14-3. 16-Bit Bus Width Byte Enable Encodings ............14-8 Table 14-4.
Page 23 Table 14-7. Summary of Short Word Load and Store Accesses ........14-23 Table 14-8. Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4) ....... 14-24 Table 14-9. Byte Ordering on Bus Transfers, Word Data Type .......... 14-28 Table 14-10.
Page 25 INTRODUCTION...
Page 27 CHAPTER 1 INTRODUCTION ® The i960 Jx microprocessor provides a new set of essential enhancements for an emerging class of high-performance embedded applications. Based on the i960 core architecture, it is implemented in a proven 0.6 micron, three-layer metal process. Figure 1-1 identifies the processor’s most notable features, each of which is described in subsections that follow the figure.
Page 28: Product Features
INTRODUCTION PRODUCT FEATURES The i960 Jx processor brings many enhancements to the i960 microprocessor family, including: • Improvements to the core architecture • Low power mode • New instructions • Improved cache design • Enhanced bus control unit • Improved interrupt performance •...
Page 29: Local Register Cache
INTRODUCTION The i960 processor compilers can take advantage of the internal data RAM; profiling compilers can allocate the most frequently used variables into this RAM. See Section 4.1, INTERNAL DATA RAM (pg. 4-1) for more detail. 1.1.4 Local Register Cache The processor provides fast storage of local registers for call and return operations by using an internal local register cache.
Page 30: Timer Support
INTRODUCTION The i960 Jx processor has approximately 5 to 10 times faster interrupt servicing than the i960 Kx processor. This is accomplished through a number of features: • a hardware priority resolver removes the need to access the external interrupt table to resolve interrupts •...
Page 31: Complete Fault Handling And Debug Capabilities
1.1.9 Complete Fault Handling and Debug Capabilities To aid in program development, the i960 Jx processor detects faults (exceptions). When a fault is detected, the processors make an implicit call to a fault handling routine. Information collected for each fault allows a program developer to quickly correct faulting code. The processors also allow automatic recovery from most faults.
Page 32: Notation And Terminology
• Part II - System Implementation (chapters 11-17) identifies requirements for designing a system around the i960 Jx components, such as external bus interface and interrupt controller. Also described are programming requirements for the bus controller and processor initialization. •...
Page 33: Specifying Bit And Signal Values
INTRODUCTION Certain areas of memory may be referred to as reserved memory in this reference manual. Reserved — when referring to memory locations — implies that an implementation of the i960 architecture may use this memory for some special purpose. For example, memory-mapped peripherals might be located in reserved memory areas on future implementations.
Page 34: Related Documents
“PFP.rt0”. RELATED DOCUMENTS The following documents are useful when designing with and programming the i960 micropro- cessor. Check the Intel website or contact your local sales representative for more information on obtaining Intel documents, including Specification Updates. •...
Page 35 DATA TYPES AND MEMORY ADDRESSING MODES...
Page 37: Data Types
CHAPTER 2 DATA TYPES AND MEMORY ADDRESSING MODES DATA TYPES ® The instruction set references or produces several data lengths and formats. The i960 processor supports the following data types: • Integer (signed 8, 16 and 32 bits) • Ordinal (unsigned integer 8, 16, 32 and 64 bits) •...
Page 38: Integers
DATA TYPES AND MEMORY ADDRESSING MODES 2.1.1 Integers Integers are signed whole numbers that are stored and operated on in two’s complement format by the integer instructions. Most integer instructions operate on 32-bit integers. Byte and short integers are referenced by the byte and short classes of the load, store and compare instructions only. Integer load or store size (byte, short or word) determines how sign extension or data truncation is performed when data is moved between registers and memory.
Page 39: Bits And Bit Fields
DATA TYPES AND MEMORY ADDRESSING MODES Sign and sign extension are not considered when ordinal loads and stores are performed; the values may, however, be zero-extended or truncated. A short word or byte load to a register causes the value loaded to be zero-extended to 32 bits. A short word or byte store to memory truncates an ordinal value in a register to fit the size of the destination memory.
Page 40: Literals
2.2.2 Byte Ordering The i960 Jx processor can be programmed to use little or big endian byte ordering for memory accesses. Byte ordering refers to how data items larger than one byte are assembled: •...
Page 41: Table 2-1. Memory Contents For Little And Big Endian Example
0. The most significant bit is always bit 31 for words, bit 15 for short words, and bit 7 for bytes. Byte ordering affects the way the i960 Jx processor handles bus accesses. See section 13.6.2, “Selecting the Byte Order” (pg. 13-12) for more information.
Page 42: Figure 2-2. Data Placement In Registers
DATA TYPES AND MEMORY ADDRESSING MODES 24 23 16 15 Byte 24 23 16 15 Short 24 23 16 15 Word NOTES: D’s are data transferred to/from memory X’s are zeros for ordinal data X’s are sign bit extensions for integer data Figure 2-2.
Page 43: Absolute
DATA TYPES AND MEMORY ADDRESSING MODES Table B-9 APPENDIX B for more on addressing modes. For purposes of this memory addressing modes description, MEMA format instructions require one word of memory and MEMB usually require two words and therefore consume twice the bus bandwidth to read. Otherwise, both formats perform the same functions.
Page 44: Index With Displacement
DATA TYPES AND MEMORY ADDRESSING MODES At the assembly language level, the assembler allows the offset to be specified with an expression or symbolic label, then evaluates the address to determine whether to use register-indirect-with- offset (MEMA format) or register-indirect-with-displacement (MEMB format) addressing mode. Register-indirect-with-index-and-displacement addressing mode adds both a scaled index and a displacement to the address base.
Page 45 DATA TYPES AND MEMORY ADDRESSING MODES g4,xyz # Absolute; word from g4 stored at memory # location designated with label xyz. ldob (r3),r4 # Register indirect; ordinal byte from # memory location given in r3 loaded # into register r4 and zero extended. g6,xyz(g5) # Register indirect with displacement;...
Page 47 PROGRAMMING ENVIRONMENT...
Page 49: Overview
REGISTERS AND LITERALS AS INSTRUCTION OPERANDS With the exception of a few special instructions, the i960 Jx processor uses load and store instruc- tions to access memory. All operations take place at the register level. The processor uses 16 global registers, 16 local registers and 32 literals (constants 0-31) as instruction operands.
Page 50: Figure 3-1. I960 ® Jx Processor Programming Environment Elements
PROGRAMMING ENVIRONMENT FFFF FFFFH 0000 0000H Address Space Architecturally Defined Data Structures Fetch Instruction Cache Load Store Instruction Stream Instruction Execution Processor State Sixteen 32-Bit Registers Global Registers Instruction Register Cache Pointer Arithmetic Sixteen 32-Bit Controls Local Registers Process Controls Trace Controls ®...
Page 51: Local Registers
PROGRAMMING ENVIRONMENT Table 3-1. Registers and Literals Used as Instruction Operands Instruction Operand Register Name (number) Function Acronym g0 - g14 global (g0-g14) general purpose global (g15) frame pointer local (r0) previous frame pointer local (r1) stack pointer local (r2) return instruction pointer r3 - r15 local (r3-r15)
Page 52: Register Scoreboarding
PROGRAMMING ENVIRONMENT 3.2.3 Register Scoreboarding Register scoreboarding maintains register coherency by preventing parallel execution units from accessing registers for which there is an outstanding operation. When an instruction that targets a destination register or group of registers executes, the processor sets a register-scoreboard bit to indicate that this register or group of registers is being used in an operation.
Page 53: Table 3-2. Allowable Register Operands
PROGRAMMING ENVIRONMENT In cases where an instruction specifies a register number and multiple consecutive registers are implied, the register number must be even when two registers are accessed (e.g., g0, g2) and an integral multiple of 4, when 3 or 4 registers are accessed (e.g., g0, g4). When a register reference for a source value is not properly aligned, the source value is undefined and an OPERATION.INVALID_OPERAND fault is generated.
Page 54: Memory-Mapped Control Registers
IPND and IMSK registers in an atomic manner on the i960 Jx processor. Do not use these instruction on any other memory-mapped registers. instruction can also modify the contents of a memory-mapped register atomically; in...
Page 55: Access Faults
PROGRAMMING ENVIRONMENT At initialization, the control table automatically loads into the on-chip control registers. This action simplifies the user’s start-up code by providing a transparent setup of the processor’s peripherals. CHAPTER 12, INITIALIZATION AND SYSTEM REQUIREMENTS. 3.3.1.2 Access Faults Memory-mapped registers are meant to be accessed only as aligned, word-size registers with adherence to the appropriate access mode.
Page 56: Table 3-3. Access Types
PROGRAMMING ENVIRONMENT Table 3-3. Access Types Access Type Description Read Read (ld instruction) accesses are allowed. Read Only Read (ld instruction) accesses are allowed. Write (st Only instruction) accesses are ignored. Write Write (st instruction) accesses allowed. Read/Write ld, st, and sysctl instructions are allowed access. Writing or Modifying (through a st or sysctl instruction) the register is only allowed when modification-rights to the register have been Write...
Page 57: Table 3-4. Supervisor Space Family Registers
PROGRAMMING ENVIRONMENT (Sheet 1 of 2) Table 3-4. Supervisor Space Family Registers Memory-Mapped Register Name Access Type Address FF00 8000H to Reserved — FF00 80FFH (DLMCON) Default Logical Memory Configuration FF00 8100H Register Reserved FF00 8104H — (LMADR0) Logical Memory Address Register 0 FF00 8108H (LMMR0) Logical Memory Mask Register 0 FF00 810CH...
Page 58 FF00 86FCH (PRCB) Processor Control Block Pointer FF00 8700H (ISP) Interrupt Stack Pointer FF00 8704H (SSP) Supervisor Stack Pointer FF00 8708H Reserved FF00 870CH — (DEVICEID) i960 Jx processor Device ID FF00 8710H FF00 8714H to Reserved — FFFF FFFFH 3-10...
Page 59: Architecturally Defined Data Structures
The i960 Jx processor defines two initialization data structures: the Initialization Boot Record (IBR) and the Process Control Block (PRCB). These structures provide initialization data and pointers to other data structures in memory.
Page 60: Table 3-6. Data Structure Descriptions
PROGRAMMING ENVIRONMENT Table 3-6. Data Structure Descriptions Structure (see also) Description User and Supervisor Stacks The processor uses these stacks when executing application section 7.6, “USER AND code. SUPERVISOR STACKS” (pg. 7-19) Interrupt Stack A separate interrupt stack is provided to ensure that interrupt section 11.5, “INTERRUPT handling does not interfere with application programs.
Page 61: Figure 3-2. Memory Address Space
PROGRAMMING ENVIRONMENT MEMORY ADDRESS SPACE The i960 Jx processor’s address space is byte-addressable with addresses running contiguously from 0 to 2 -1. Some memory space is reserved or assigned special functions as shown in Figure 3-2. Address NMI Vector 0000 0000H...
Page 62: Memory Requirements
Jx processor’s reserved memory. The i960 Jx processor requires some special consideration when using the lower 1 Kbyte of address space (addresses 0000H to 03FFH). Loads and stores directed to these addresses access internal memory;...
Page 63: Data And Instruction Alignment In The Address Space
) to word boundaries in memory. atadd atmod The i960 Jx processor can perform unaligned load or store accesses. The processor handles a non-aligned load or store request by: • Automatically servicing a non-aligned memory access with microcode assistance as described section 13.5.2, “Bus Transactions Across Region Boundaries”...
Page 64: Internal Data Ram
This method of ordering bytes in memory is referred to as “little endian” ordering. The i960 Jx processor also provides an option for ordering bytes in the opposite manner in memory. The block’s most significant byte is stored at the base address and the less significant bytes are stored at successively higher addresses.
Page 65: Data Cache
RAM. LOCAL REGISTER CACHE The i960 Jx processor provides fast storage of local registers for call and return operations by using an internal local register cache (also known as a stack frame cache). Up to 7 local register sets can be contained in the cache before sets must be saved in external memory.
Page 66: Initializing And Modifying The Ac Register
PROGRAMMING ENVIRONMENT 3.7.2 Arithmetic Controls (AC) Register The AC register (Figure 3-3) contains condition code flags, integer overflow flag, mask bit and a bit that controls faulting on imprecise faults. Unused AC register bits are reserved. No-Imprecise-Faults Bit- AC.nif (0) Some Faults are Imprecise (1) All Faults are Precise Integer Overflow Mask Bit - AC.om (0) No Mask...
Page 67: Condition Code (Ac.cc)
The term unordered is used when comparing floating point numbers. The i960 Jx processor does not implement on-chip floating point processing. To show carry out and overflow, the processor sets the condition code flags as shown in Table 3-10.
Page 68 PROGRAMMING ENVIRONMENT Certain instructions, such as the branch-if instructions, use a 3-bit mask to evaluate the condition code flags. For example, the branch-if-greater-or-equal instruction ( ) uses a mask of 011 determine if the condition code is set to either greater-than or equal. Conditional instructions use similar masks for the remaining conditions such as: greater-or-equal (011 ), less-or-equal (110 and not-equal (101...
Page 69: Figure 3-4. Process Controls (Pc) Register
PROGRAMMING ENVIRONMENT 3.7.3 Process Controls (PC) Register The PC register (Figure 3-4) is used to control processor activity and show the processor’s current state. The PC register execution mode flag (bit 1) indicates that the processor is operating in either user mode (0) or supervisor mode (1).
Page 70: Initializing And Modifying The Pc Register
PROGRAMMING ENVIRONMENT The processor uses the priority field to determine whether to service an interrupt immediately or to post the interrupt. The processor compares the priority of a requested interrupt with the current process priority. When the interrupt priority is greater than the current process priority or equal to 31, the interrupt is serviced;...
Page 71: Trace Controls (Tc) Register
PROGRAMMING ENVIRONMENT 3.7.4 Trace Controls (TC) Register The TC register, in conjunction with the PC register, controls processor tracing facilities. It contains trace mode enable bits and trace event flags that are used to enable specific tracing modes and record trace events, respectively.
Page 72: Using The User-Supervisor Protection Model
PROGRAMMING ENVIRONMENT 3.8.2 Using the User-Supervisor Protection Model A program switches from user mode to supervisor mode by making a system-supervisor call (also referred to as a supervisor call). A system-supervisor call is a call executed with the call-system instruction ( calls ).
Page 73 CACHE AND ON-CHIP DATA...
Page 75: Internal Data Ram
CHAPTER 4 CACHE AND ON-CHIP DATA RAM This chapter describes the structure and user configuration of all forms of on-chip storage, including caches (data, local register and instruction) and data RAM. INTERNAL DATA RAM Internal data RAM is mapped to the lower 1 Kbyte (0 to 03FFH) of the address space. Loads and stores with target addresses in internal data RAM operate directly on the internal data RAM;...
Page 76: Figure 4-1. Internal Data Ram And Register Cache
Some versions of i960 processor compilers can take advantage of internal data RAM. Profiling compilers, such as those offered by Intel, can allocate the most frequently used variables into this RAM. LOCAL REGISTER CACHE The i960 Jx processor provides fast storage of local registers for call and return operations by using an internal local register cache (also known as a stack frame cache).
Page 77 CACHE AND ON-CHIP DATA RAM The branch-and-link ( balx ) instructions do not cause the local registers to be stored. The entire internal register cache contents can be copied to the external procedure stack through the instruction. Section 6.2.30, flushreg (pg. 6-54) explains the instruction and section 7.2, flushreg...
Page 78: Big Endian Accesses To Internal Ram And Data Cache
BIG ENDIAN ACCESSES TO INTERNAL RAM AND DATA CACHE The i960 Jx processor supports big-endian accesses to the internal data RAM and data cache. The default byte order for data accesses is programmed in DLMCON.be as either little or big-endian.
Page 79: Operation While The Instruction Cache Is Disabled
The block size that can be loaded and locked on the i960 Jx processor is one way of the cache. Any code can be locked into the cache, not just interrupt routines.
Page 80: Enabling And Disabling The Data Cache
To achieve cache coherency, instruction cache contents should be invalidated after code modification is complete. The instruction icctl invalidates the instruction cache for the i960 Jx processor. Alternately, legacy software can use the sysctl instruction. DATA CACHE The i960 JT processor features a 4 Kbyte direct-mapped data cache.
Page 81: Multi-Word Data Accesses That Partially Hit The Data Cache
CACHE AND ON-CHIP DATA RAM 4.5.2 Multi-Word Data Accesses that Partially Hit the Data Cache The following applies only when data caching is enabled for an access. For a multi-word load access ( ) in which none of the requested words hit the data cache, an external bus transaction is started to acquire all the words of the access.
Page 82: Data Cache Fill Policy
The i960 Jx processor always uses a write-allocate policy for data. For a cacheable location, data is always written to the data cache regardless of whether the access is a hit or miss. The following...
Page 83: Data Cache Coherency And Non-Cacheable Accesses
4.5.5 Data Cache Coherency and Non-Cacheable Accesses The i960 Jx processor ensures that the data cache is always kept coherent with accesses that it initiates and performs. The most visible application of this requirement concerns non-cacheable accesses discussed below. However, the processor does not provide data-cache coherency for accesses on the external bus that it did not initiate.
Page 84: External I/O And Bus Masters And Cache Coherency
4.5.6 External I/O and Bus Masters and Cache Coherency The i960 Jx processor implements a single processor coherency mechanism. There is no hardware mechanism, such as bus snooping, to support multiprocessing. When another bus master can change shared memory, there is no guarantee that the data cache contains the most recent data. The user must manage such data coherency issues in software.
Page 85 INSTRUCTION SET OVERVIEW...
Page 87: Instruction Formats
INSTRUCTION FORMATS The i960 Jx processor instructions may be described in two formats: assembly language and instruction encoding. The following subsections briefly describe these formats. 5.1.1 Assembly Language Format Throughout this manual, instructions are referred to by their assembly language mnemonics.
Page 88: Table 5-1. Instruction Encoding Formats
INSTRUCTION SET OVERVIEW 5.1.2 Instruction Encoding Formats All instructions are encoded in one 32-bit machine language instruction — also known as an opword — which must be word aligned in memory. An opword’s most significant eight bits contain the opcode field. The opcode field determines the instruction to be performed and how the remainder of the machine language instruction is interpreted.
Page 89: Instruction Operands
INSTRUCTION SET OVERVIEW OPCODE OPCODE src1 src/dst src2 COBR displacement OPCODE src1 src2 OPCODE displacement CTRL Address OPCODE src/dst Offset MEMA Base Address src/dst OPCODE Scale Index MEMB Base 32-Bit displacement Figure 5-1. Machine-Level Instruction Formats 5.1.3 Instruction Operands This section identifies and describes operands that can be used with the instruction formats. Format Operand(s) Description...
Page 90: Instruction Groups
INSTRUCTION SET OVERVIEW INSTRUCTION GROUPS The following sections provide an overview of the instructions in each group. For detailed information about each instruction, refer to CHAPTER 6, INSTRUCTION SET REFERENCE. The i960 processor instruction set can be categorized into functional groups shown in Table 5-2.
Page 91: Data Movement
INSTRUCTION SET OVERVIEW 5.2.1 Data Movement These instructions are used to: • move data from memory to global and local registers • from global and local registers to memory • between local and global registers Rules for register alignment must be followed when using load, store and move instructions that move 8, 12 or 16 bytes at a time.
Page 92: Move
INSTRUCTION SET OVERVIEW stob stos stib stis , the instruction specifies a memory address and register; the register value is copied into memory. For byte and short instructions, the processor automatically reformats the source register’s 32-bit value for the shorter memory location. For , this stib stis...
Page 93: Table 5-3. Arithmetic Operations
Arithmetic Table 5-3 lists arithmetic operations and data types for which the i960 Jx processor provides instructions. “X” in this table indicates that the microprocessor provides an instruction for the specified operation and data type. All arithmetic operations are carried out on operands in registers or literals.
Page 94: Add, Subtract, Multiply, Divide, Conditional Add, Conditional Subtract
INSTRUCTION SET OVERVIEW 5.2.3.1 Add, Subtract, Multiply, Divide, Conditional Add, Conditional Subtract These instructions perform add, subtract, multiply or divide operations on integers and ordinals: addi Add Integer addo Add Ordinal ADD <cc> conditional add subi Subtract Integer subo Subtract Ordinal SUB<cc>...
Page 95: Shift, Rotate And Extended Shift
INSTRUCTION SET OVERVIEW 5.2.3.3 Shift, Rotate and Extended Shift These shift instructions shift an operand a specified number of bits left or right: shlo shift left ordinal shro shift right ordinal shli shift left integer shri shift right integer shrdi shift right dividing integer rotate rotate left...
Page 96: Extended Arithmetic
INSTRUCTION SET OVERVIEW 5.2.3.4 Extended Arithmetic These instructions support extended-precision arithmetic; i.e., arithmetic operations on operands greater than one word in length: addc add ordinal with carry subc subtract ordinal with carry emul extended multiply ediv extended divide addc adds two word operands (literals or contained in registers) plus the AC Register condition code bit 1 (used here as a carry bit).
Page 97: Bit, Bit Field And Byte Operations
INSTRUCTION SET OVERVIEW 5.2.5 Bit, Bit Field and Byte Operations These instructions perform operations on a specified bit or bit field in an ordinal operand. All Bit, Bit Field and Byte instructions use the REG format and can operate on literals or local or global registers. 5.2.5.1 Bit Operations These instructions operate on a specified bit:...
Page 98: Comparison
INSTRUCTION SET OVERVIEW 5.2.6 Comparison The processor provides several types of instructions for comparing two operands, as described in the following subsections. 5.2.6.1 Compare and Conditional Compare These instructions compare two operands then set the condition code bits in the AC register according to the results of the comparison: cmpi Compare Integer...
Page 99: Compare And Increment Or Decrement
INSTRUCTION SET OVERVIEW 5.2.6.2 Compare and Increment or Decrement These instructions compare two operands, set the condition code bits according to the compare results, then increment or decrement one of the operands: cmpinci compare and increment integer cmpinco compare and increment ordinal cmpdeci compare and decrement integer cmpdeco...
Page 100: Branch
INSTRUCTION SET OVERVIEW 5.2.7 Branch Branch instructions allow program flow direction to be changed by explicitly modifying the IP. The processor provides three branch instruction types: • unconditional branch • conditional branch • compare and branch Most branch instructions specify the target IP by specifying a signed displacement to be added to the current IP.
Page 101: Conditional Branch
INSTRUCTION SET OVERVIEW 5.2.7.2 Conditional Branch With conditional branch ( ) instructions, the processor checks the AC register condition BRANCH IF code flags. When these flags match the value specified with the instruction, the processor jumps to the target IP. These instructions use the displacement-plus-ip method of specifying the target IP: branch if equal/true branch if not equal branch if less...
Page 102: Call/Return
5.2.8 Call/Return The i960 Jx processor offers an on-chip call/return mechanism for making procedure calls. Refer section 7.1, “CALL AND RETURN MECHANISM” (pg. 7-2). The following instructions support this mechanism:...
Page 103: Faults
INSTRUCTION SET OVERVIEW Depending on the type of entry being pointed to in the system procedure table, calls can cause either a system-supervisor call or a system-local call to be executed. A system-supervisor call is a call to a system procedure that switches the processor to supervisor mode and switches to the supervisor stack.
Page 104: Debug
This instruction is used, in part, to load and control the i960 Jx processor’s breakpoint registers. 5.2.11 Atomic Instructions Atomic instructions perform an atomic read-modify-write operation on operands in memory. An atomic operation is one in which other memory operations are forced to occur before or after, but not during, the accesses that comprise the atomic operation.
Page 105: Processor Management
INSTRUCTION SET OVERVIEW 5.2.12 Processor Management These instructions control processor-related functions: modpc Modify the Process Controls register flushreg Flush cached local register sets to memory modac Modify the Arithmetic Controls register sysctl Perform system control function halt Halt processor inten Global interrupt enable intdis Global interrupt disable...
Page 106: Performance Optimization
5.3.1.1 Load / Store Execution Model Because the i960 Jx processor has a 32-bit external data bus, multiple word accesses require multiple cycles. The processor uses microcode to sequence the multi-word accesses. Because the microcode can ensure that aligned multi-words are bursted together on the external bus, software should not substitute multiple single-word instructions for one multi-word instruction for data that is not likely to be in cache.
Page 107: Microcoded Instructions
5.3.1.3 Microcoded Instructions While the majority of instructions on the i960 Jx processor are single cycle and are executed directly by processor hardware, some require microcode emulation. Entry into a microcode routine requires two cycles. Exit from microcode typically requires two cycles. For some routines, one cycle of the exit process can execute in parallel with another instruction, thus saving one cycle of execution time.
Page 108: Simple Control Transfer
5.3.1.6 Simple Control Transfer There is no branch lookahead or branch prediction mechanism on the i960 Jx processor. Simple branch instructions take one cycle to execute, and one more cycle is needed to fetch the target instruction when the branch is actually taken.
Page 109: Unaligned Memory Accesses
INSTRUCTION SET OVERVIEW 5.3.1.8 Unaligned Memory Accesses Unaligned memory accesses are performed by microcode. Microcode sequences the access into smaller aligned pieces and merges the data as needed. As a result, these accesses are not as efficient as aligned accesses. In addition, no bursting on the external bus is performed for these accesses. Whenever possible, unaligned accesses should be avoided.
Page 110: Execute In Imprecise Fault Mode
INSTRUCTION SET OVERVIEW 5.3.2.4 Execute in Imprecise Fault Mode Significant performance improvement is possible by allowing imprecise faults (AC.nif = 0). In precise fault mode (AC.nif = 1), the processor does not issue a new instruction until the previous one has completed. This ensures that a fault from the previous instruction is delivered before the next instruction can begin execution.
Page 111 INSTRUCTION SET REFERENCE...
Page 113: Notation
6.1, “NOTATION” (pg. 6-1). Information in this chapter is oriented toward programmers who write assembly language code for the i960 Jx processor. Information provided for each instruction includes: • Alphabetic listing of all instructions •...
Page 114: Alphabetic Reference
BRANCH<cc> FAULT<cc> The i960 Jx processor-specific extensions to the i960 microprocessor instruction set are indicated in the header text for each such instruction. This type of notation is also used to indicate new core architecture instructions. Sections describing new core instructions provide notes as to which i960-series processors do not implement these instructions.
Page 115: Description
INSTRUCTION SET REFERENCE Global (g0 ... g15) or local (r0 ... r15) register Literal of the range 0 ... 31 disp Signed displacement of range (-2 ... 2 - 1) mem Address defined with the full range of addressing modes In some cases, a third line is added to show register or memory location contents.
Page 116: Table 6-1. Pseudo-Code Symbol Definitions
INSTRUCTION SET REFERENCE Table 6-1. Pseudo-Code Symbol Definitions Assignment ==, != Comparison: equal, not equal <, > less than, greater than <=, >= less than or equal to, greater than or equal to <<, >> Logical Shift Exponentiation &, && Bitwise AND, logical AND |, || Bitwise OR, logical OR...
Page 117: Example
INSTRUCTION SET REFERENCE Table 6-3. Common Faulting Conditions Fault Type Subtype Description Any instruction that causes an unaligned memory access causes an operation aligned fault when unaligned faults are UNALIGNED not masked in the fault configuration word in the Processor Control Block (PRCB).
Page 118: Opcode And Instruction Format
INSTRUCTION SET REFERENCE 6.1.8 Opcode and Instruction Format The Opcode and Instruction Format section gives the opcode and instruction format for each instruction, for example: 593H subi The opcode is given in hexadecimal format. The format is one of four possible formats: REG, COBR, CTRL and MEM.
Page 119: Add
INSTRUCTION SET REFERENCE 6.2.1 ADD<cc> Add Ordinal if Unordered Mnemonic: addono Add Ordinal if Greater addog Add Ordinal if Equal addoe Add Ordinal if Greater or Equal addoge addol Add Ordinal if Less addone Add Ordinal if Not Equal Add Ordinal if Less or Equal addole Add Ordinal if Ordered addoo...
Page 120: Table 6-5. Condition Code Mask Descriptions
INSTRUCTION SET REFERENCE Table 6-4. Condition Code Mask Descriptions Instruction Mask Condition addone Not equal addine addole Less or equal addile addoo Ordered addio Action: addo<cc>: if((mask & AC.cc) || (mask == AC.cc)) dst = (src1 + src2)[31:0]; addi<cc>: if((mask & AC.cc) || (mask == AC.cc)) true_result = (src1 + src2);...
Page 121 INSTRUCTION SET REFERENCE Opcode: addono 780H 790H addog 7A0H addoe 7B0H addoge 7C0H addol addone 7D0H addole 7E0H addoo 7F0H 781H addino 791H addig 7A1H addie 7B1H addige addil 7C1H addine 7D1H 7E1H addile 7F1H addio See Also: addc, SUB<cc>, addi, addo This class of core instructions is not implemented on 80960Cx, Kx and Sx Notes: processors.
Page 122: Addc
INSTRUCTION SET REFERENCE 6.2.2 addc Add Ordinal With Carry Mnemonic: addc src1, src2, Format: addc reg/lit reg/lit Description: Adds src2 and src1 values and condition code bit 1 (used here as a carry-in) and stores the result in dst. When ordinal addition results in a carry out, condition code bit 1 is set;...
Page 123: Addi, Addo
INSTRUCTION SET REFERENCE 6.2.3 addi, addo Add Ordinal Mnemonic: addo Add Integer addi src1, src2, Format: add* reg/lit reg/lit Description: Adds src2 and src1 values and stores the result in dst. The binary results from these two instructions are identical. The only difference is that can signal addi an integer overflow.
Page 124: Alterbit
INSTRUCTION SET REFERENCE 6.2.4 alterbit Alter Bit Mnemonic: alterbit bitpos, src, Format: alterbit reg/lit reg/lit Description: Copies src value to dst with one bit altered. bitpos operand specifies bit to be changed; condition code determines the value to which the bit is set. When condition code is X1X , bit 1 = 1, the selected bit is set;...
Page 125: And, Andnot
INSTRUCTION SET REFERENCE 6.2.5 and, andnot Mnemonic: And Not andnot src1, src2, Format: reg/lit reg/lit andnot src1, src2, reg/lit reg/lit Performs a bitwise AND ( ) or AND NOT ( ) operation on src2 and Description: andnot src1 values and stores result in dst. Note in the action expressions below, src2 operand comes first, so that with the expression is evaluated as: andnot...
Page 126: Atadd
INSTRUCTION SET REFERENCE 6.2.6 atadd Atomic Add Mnemonic: atadd addr, src, Format: atadd reg/lit Description: Adds src value (full word) to value in the memory location specified with addr operand. This read-modify-write operation is performed on the actual data in memory and never on a cached value on chip. Initial value from memory is stored in dst.
Page 127: Atmod
INSTRUCTION SET REFERENCE 6.2.7 atmod Atomic Modify Mnemonic: atmod addr, mask, src/dst Format: atmod reg/lit Description: Copies the selected bits of src/dst value into memory location specified in addr. The read-modify-write operation is performed on the actual data in memory and never on a cached value on chip. Bits set in mask operand select bits to be modified in memory.
Page 128 IP specified with targ operand can be no farther than to (2 - 4) bytes from current IP. When using the Intel i960 processor assembler, targ operand must be a label which specifies target instruction’s performs the same operation as...
Page 129: Bal, Balx
-2 to (2 - 4) bytes from current IP. When using the Intel i960 processor assembler, targ must be a label which specifies the target instruction’s IP. performs same operation as except next instruction address is stored balx in dst (allowing the return IP to be stored in any available register).
Page 130 INSTRUCTION SET REFERENCE Faults: STANDARD Refer to section 6.1.6, “Faults” (pg. 6-5). Example: bal xyz # g14 IP + 4 # IP balx (g2), g4 # g4 IP + 4 # IP (g2) CTRL Opcode: balx See Also: b, bx, BRANCH<cc>, COMPARE AND BRANCH<cc>, bbc, bbs 6-18...
Page 131: Bbc, Bbs
-2 to (2 - 4) bytes from current IP. When using the Intel i960 processor assembler, targ must be a label which specifies target instruction’s IP. Action: bbs: if((src & 2**(bitpos%32)) == 1) AC.cc = 010...
Page 132 INSTRUCTION SET REFERENCE Example: # Assume bit 10 of r6 is clear. bbc 10, r6, xyz # Bit 10 of r6 is checked # and found clear: # AC.cc # IP xyz; COBR Opcode: COBR See Also: chkbit, COMPARE AND BRANCH<cc>, BRANCH<cc> Sets the condition code in the arithmetic controls.
Page 133: Branch
INSTRUCTION SET REFERENCE 6.2.11 BRANCH<cc> Branch If Equal Mnemonic: Branch If Not Equal Branch If Less Branch If Less Or Equal Branch If Greater Branch If Greater Or Equal Branch If Ordered Branch If Unordered targ Format: disp Description: Branches to instruction specified with targ operand according to AC register condition code state.
Page 134 INSTRUCTION SET REFERENCE Action: if((mask & AC.cc) || (mask == AC.cc)) temp[31:2] = sign_extension(targ[23:2]); IP[31:2] = IP[31:2] + temp[31:2]; IP[1:0] = 0; Faults: STANDARD Refer to section 6.1.6, “Faults” (pg. 6-5). Example: # Assume (AC.cc AND 100 bl xyz # IP xyz;...
Page 135: Bswap
INSTRUCTION SET REFERENCE 6.2.12 bswap Byte Swap Mnemonic: bswap src, Format: bswap reg/lit Description: Alters the order of bytes in a word, reversing its “endianess.” Copies bytes 3:0 of src to dst reversing order of the bytes. Byte 0 of src becomes byte 3 of dst, byte 1 of src becomes byte 2 of dst, etc.
Page 136: Call
Description: Calls a new procedure. targ operand specifies the IP of called procedure’s first instruction. When using the Intel i960 processor assembler, targ must be a label. In executing this instruction, the processor performs a local call operation as described in section 7.1.3.1, “Call Operation”...
Page 137: Calls
# Local call or supervisor call from supervisor mode. tempa = (SP + (SALIGN*16 - 1)) & ~(SALIGN*16 - 1) # Round stack pointer to next boundary. # SALIGN=1 on i960 Jx processors. temp.RRR = 000 else # Supervisor call from user mode.
Page 138 INSTRUCTION SET REFERENCE tempa = SSP; # Get Supervisor Stack pointer. temp.RRR = 010 | PC.te; PC.em = supervisor; PC.te = temp.te; PFP = FP; PFP.rrr = temp.RRR; FP = tempa; SP = tempa + 64; STANDARD Refer to section 6.1.6, “Faults” (pg. 6-5).
Page 139: Callx
Wait for any uncompleted instructions to finish; Action: implicit_syncf(); temp = (SP + (SALIGN*16 - 1)) & ~(SALIGN*16 - 1) # Round stack pointer to next boundary. # SALIGN=1 on i960 Jx processors. if (register_set_available) allocate_new_frame( ); else save_register_set( );...
Page 140 INSTRUCTION SET REFERENCE Example: callx (g5) # IP (g5), where the address in g5 # is the address of the new procedure. Opcode: callx See Also: bal, call, calls, ret 6-28...
Page 141: Chkbit
INSTRUCTION SET REFERENCE 6.2.16 chkbit Check Bit Mnemonic: chkbit bitpos, src2 Format: chkbit reg/lit reg/lit Description: Checks bit in src2 designated by bitpos and sets condition code according to value found. When bit is set, condition code is set to 010 ;...
Page 142: Clrbit
INSTRUCTION SET REFERENCE 6.2.17 clrbit Clear Bit Mnemonic: clrbit bitpos, src, Format: clrbit reg/lit reg/lit Description: Copies src value to dst with one bit cleared. bitpos operand specifies bit to be cleared. dst = src & ~(2**(bitpos%32)); Action: STANDARD Refer to section 6.1.6, “Faults”...
Page 143: Cmpdeci, Cmpdeco
INSTRUCTION SET REFERENCE 6.2.18 cmpdeci, cmpdeco Compare and Decrement Integer Mnemonic: cmpdeci Compare and Decrement Ordinal cmpdeco src1, src2, Format: cmpdec reg/lit reg/lit Description: Compares src2 and src1 values and sets the condition code according to comparison results. src2 is then decremented by one and result is stored in dst.
Page 144: Cmpinci, Cmpinco
INSTRUCTION SET REFERENCE 6.2.19 cmpinci, cmpinco Compare and Increment Integer Mnemonic: cmpinci Compare and Increment Ordinal cmpinco src1, src2, Format: cmpinc reg/lit reg/lit Description: Compares src2 and src1 values and sets the condition code according to comparison results. src2 is then incremented by one and result is stored in dst.
Page 145: Compare
INSTRUCTION SET REFERENCE 6.2.20 COMPARE Compare Integer Mnemonic: cmpi Compare Integer Byte cmpib Compare Integer Short cmpis Compare Ordinal cmpo cmpob Compare Ordinal Byte cmpos Compare Ordinal Short src1, src2 Format: reg/lit reg/lit Description: Compares src2 and src1 values and sets condition code according to comparison results.
Page 146 INSTRUCTION SET REFERENCE Example: cmpo r9, 0x10 # Compares the value in r9 with 0x10 # and sets AC.cc to indicate the # result. bg xyz # Branches to xyz if the value of r9 # was greater than 0x10. 5A1H Opcode: cmpi...
Page 147: Compare And Branch
-2 to (2 - 4) bytes from current IP. When using the Intel i960 processor assembler, targ must be a label which specifies target instruction’s IP. Functions these instructions perform can be duplicated with a...
Page 148: Table 6-9. Condition Code Mask Descriptions
INSTRUCTION SET REFERENCE The following table shows the condition code mask for each instruction. The mask is in bits 0-2 of the opcode. Table 6-9. Condition Code Mask Descriptions Branch Instruction Mask Condition cmpibno No Condition cmpibg src1 > src2 cmpibe src1 = src2 cmpibge...
Page 149 INSTRUCTION SET REFERENCE Opcode: cmpibe COBR COBR cmpibne COBR cmpibl COBR cmpible COBR cmpibg cmpibge COBR cmpibo COBR cmpibno COBR COBR cmpobe COBR cmpobne COBR cmpobl COBR cmpoble cmpobg COBR cmpobge COBR cmpo balx See Also: BRANCH<cc>, cmpi, Side Effects: Sets the condition code in the arithmetic controls.
Page 150: Concmpi, Concmpo
INSTRUCTION SET REFERENCE 6.2.22 concmpi, concmpo Conditional Compare Integer Mnemonic: concmpi Conditional Compare Ordinal concmpo src1, src2 Format: concmp* reg/lit reg/lit Description: Compares src2 and src1 values when condition code bit 2 is not set. When comparison is performed, condition code is set according to comparison results.
Page 151: Table 6-10. Concmpo Example: Register Ordering And Cc
INSTRUCTION SET REFERENCE Table 6-10. concmpo example: register ordering and CC Order g5 < g6 < g3 g5 < g6 = g3 g5 < g3 < g6 g5 = g3 < g6 g3 < g5 < g6 Opcode: concmpi 5A3H concmpo 5A2H See Also:...
Page 152: Table 6-11. Dcctl Operand Fields
INSTRUCTION SET REFERENCE 6.2.23 dcctl Data-cache Control Mnemonic: dcctl src1, src2, src/dst Format: reg/lit reg/lit Description: Performs management and control of the data cache including disabling, enabling, invalidating, ensuring coherency, getting status, and storing cache contents to memory. Operations are indicated by the value of src1. src2 and src/dst are also used by some operations.
Page 153: Figure 6-1. Dcctl Src1 And Src/Dst Formats
INSTRUCTION SET REFERENCE src1 Format Function Type src/dst Format for Data Cache Status 28 27 16 15 # of Ways-1 log2 (# of Sets) log2 (Atoms/Line) Enabled = 1 log2 (Bytes/Atom) Disabled = 0 src/dst Format for Store Data Cache Sets to Memory 16 15 Starting Set # Ending Set #...
Page 154: Figure 6-2. Store Data Cache To Memory Output Format
INSTRUCTION SET REFERENCE Table 6-12. DCCTL Status Values and D-Cache Parameters Value on Value on Value on Value i960JD/JF i960JA CPU i960JT CPU bytes per atom atoms per line number of sets 128 (full) number of ways 1 (Direct) 1 (Direct) 1 (Direct) cache size 1-Kbytes...
Page 155: Figure 6-3. D-Cache Tag And Valid Bit Formats
INSTRUCTION SET REFERENCE 80960JT Cache Tag Format (4 Kbyte Cache) 20 19 80960JT Actual Address Bits 31:12 80960JF/JD Cache Tag Format (2 Kbyte Cache) 21 20 80960JF/JD Actual Address Bits 31:11 80960JA Cache Tag Format (1 Kbyte Cache) 22 21 80960JA Actual Address Bits 31:10 Valid Bits Values Valid Bit for Word 3 of current Set and Way...
Page 156 INSTRUCTION SET REFERENCE Action: if (PC.em != supervisor) generate_fault(TYPE.MISMATCH); order_wrt(previous_operations); switch (src1[7:0]) { case 0: # Disable data cache. disable_Dcache( ); break; case 1: # Enable data cache. enable_Dcache( ); break; case 2: # Global invalidate data cache. invalidate_Dcache( ); break;...
Page 157 INSTRUCTION SET REFERENCE case 6: # Store data cache sets to memory pointed to by src2. start = src_dst[15:0] Starting set number. end = src_dst[31:16] Ending set number. (zero-origin). if (end >= Dcache_max_sets) end = Dcache_max_sets - 1; if (start > end) generate_fault (OPERATION.INVALID_OPERAND);...
Page 158 INSTRUCTION SET REFERENCE Example: # g0 = 6, g1 = 0x10000000, # g2 = 0x001F0001 dcctl g0,g1,g2 # Store the status of D-cache # sets 1-0x1F to memory starting # at 0x10000000. 65CH Opcode: dcctl See Also: sysctl DCCTL function 6 stores data-cache sets to a target range in external mem- Notes: ory.
Page 159: Divi, Divo
INSTRUCTION SET REFERENCE 6.2.24 divi, divo Divide Integer Mnemonic: divi Divide Ordinal divo src1, src2, Format: div* reg/lit reg/lit Description: Divides src2 value by src1 value and stores result in dst. Remainder is discarded. , an integer-overflow fault can be signaled. divi Action: divo:...
Page 160: Ediv
INSTRUCTION SET REFERENCE 6.2.25 ediv Extended Divide Mnemonic: ediv src1, src2, Format: ediv reg/lit reg/lit Description: Divides src2 by src1 and stores result in dst. The src2 value is a long ordinal (64 bits) contained in two adjacent registers. src2 specifies the lower numbered register which contains operand’s least significant bits.
Page 161: Emul
INSTRUCTION SET REFERENCE 6.2.26 emul Extended Multiply Mnemonic: emul src1, src2, Format: emul reg/lit reg/lit Description: Multiplies src2 by src1 and stores the result in dst. Result is a long ordinal (64 bits) stored in two adjacent registers. dst specifies lower numbered register, which receives the result’s least significant bits.
Page 162: Eshro
INSTRUCTION SET REFERENCE 6.2.27 eshro Extended Shift Right Ordinal Mnemonic: eshro src1, src2, Format: eshro reg/lit reg/lit Description: Shifts src2 right by (src1 32) places and stores the result in dst. Bits shifted beyond the least-significant bit are discarded. src2 value is a long ordinal (i.e., 64 bits) contained in two adjacent registers. src2 operand specifies the lower numbered register, which contains operand’s least significant bits.
Page 163: Extract
INSTRUCTION SET REFERENCE 6.2.28 extract Extract Mnemonic: extract bitpos src/dst Format: extract reg/lit reg/lit Description: Shifts a specified bit field in src/dst right and zero fills bits to left of shifted bit field. bitpos value specifies the least significant bit of the bit field to be shifted;...
Page 164: Fault
INSTRUCTION SET REFERENCE 6.2.29 FAULT<cc> Fault If Equal Mnemonic: faulte Fault If Not Equal faultne Fault If Less faultl Fault If Less Or Equal faultle faultg Fault If Greater faultge Fault If Greater Or Equal Fault If Ordered faulto Fault If Not Ordered faultno Format: fault...
Page 165 INSTRUCTION SET REFERENCE Faults: STANDARD Refer to section 6.1.6, “Faults” (pg. 6-5). CONSTRAINT.RANGE When condition being tested is true. Example: # Assume (AC.cc AND 110 ) 000 faultle # Generate CONSTRAINT_RANGE fault CTRL Opcode: faulte CTRL faultne CTRL faultl CTRL faultle faultg CTRL...
Page 166: Flushreg
INSTRUCTION SET REFERENCE 6.2.30 flushreg Flush Local Registers Mnemonic: flushreg Format: flushreg Description: Copies the contents of every cached register set, except the current set, to its associated stack frame in memory. The entire register cache is then marked as purged (or invalid).
Page 167: Fmark
INSTRUCTION SET REFERENCE 6.2.31 fmark Force Mark Mnemonic: fmark Format: fmark Description: Generates a mark trace event. Causes a mark trace event to be generated, regardless of mark trace mode flag setting, providing the trace enable bit, bit 0 in the Process Controls, is set. For more information on trace fault generation, refer to CHAPTER 9, TRACING AND...
Page 168: Halt
INSTRUCTION SET REFERENCE 6.2.32 halt Halt CPU Mnemonic: halt src1 Format: halt reg/lit Description: Causes the processor to enter HALT mode, which is described in. Entry into Halt mode allows the interrupt enable state to be conditionally changed based on the value of src1. Table 6.14.
Page 169 INSTRUCTION SET REFERENCE Faults: STANDARD Refer to section 6.1.6, “Faults” (pg. 6-5). TYPE.MISMATCH Attempt to execute instruction while not in supervisor mode. Example: # ICON.gie = 1, g0 = 1, Interrupts disabled. halt g0 # Enable interrupts and halt. 65DH Opcode: halt This instruction is implemented on the 80960Rx and 80960Jx processor fam-...
Page 170: Table 6-15. Icctl Operand Fields
INSTRUCTION SET REFERENCE 6.2.33 icctl Instruction-cache Control Mnemonic: icctl src1, src2, src/dst Format: icctl reg/lit reg/lit Description: Performs management and control of the instruction cache including disabling, enabling, invalidating, loading and locking, getting status, and storing cache sets to memory. Operations are indicated by the value of src1. Some operations also use src2 and src/dst.
Page 171: Figure 6-4. Icctl Src1 And Src/Dst Formats
INSTRUCTION SET REFERENCE src1 Format Function Type src/dst Format for I-cache Status 28 27 16 15 # of Ways-1 (# of Sets) (Atoms/Line) Enabled = 1 Disabled = 0 (Bytes/Atom) src/dst Format for I-cache Locking Status 24 23 # of ways that Way Size in Words # of ways that Lock are currently locked...
Page 172: Table 6-16. Icctl Status Values And Instruction Cache Parameters
INSTRUCTION SET REFERENCE Table 6-16. ICCTL Status Values and Instruction Cache Parameters Value on Value on Value on Value i960JD/JF i960JA CPU i960JTA CPU bytes per atom atoms per line number of sets number of ways cache size 2-Kbytes 4-Kbytes 16-Kbytes Status[0] (enable / 0 or 1...
Page 173: Figure 6-5. Store Instruction Cache To Memory Output Format
INSTRUCTION SET REFERENCE Destination Set_Data [Starting Set] Address (DA) Tag (Starting set) DA + 4H Valid Bits (Starting set) DA + 8H Word 0 DA + CH Word 1 DA + 10H Word 2 DA + 14H Word 3 DA + 18H Tag (Starting set) DA + 1CH Valid Bits (Starting set)
Page 174: Figure 6-6. I-Cache Set Data, Tag And Valid Bit Formats
INSTRUCTION SET REFERENCE Set Data I-Cache Values I-Cache Set Data Value 0 = Way 0 is least recently used 1 = Way 1 is least recently used 80960JT Cache Tag Format (16 Kbyte Cache) 19 18 80960JT Actual Address Bits 31:13 80960JF/JD Cache Tag Format (4 Kbyte Cache) 21 20 80960JF/JD Actual Address Bits 31:11...
Page 175 # Load & Lock code into Instruction-Cache # src_dst has number of contiguous blocks to lock. # src2 has starting address of code to lock. # On the i960 Jx, src2 is aligned to a quad word boundary aligned_addr = src2 & 0xFFFFFFF0; invalidate(I-cache); unlock(I-cache);...
Page 176 INSTRUCTION SET REFERENCE case 5: # Get instruction cache locking status into dst. src_dst[7:0] = number_of_blocks_that_lock; src_dst[23:8] = block_size_in_words; src_dst[31:24] = number_of_blocks_that_are_locked; break; case 6: # Store instr cache sets to memory pointed to by src2. start = src_dst[15:0] # Starting set number end = src_dst[31:16] # Ending set number # (zero-origin).
Page 177 INSTRUCTION SET REFERENCE Example: # g0 = 3, g1=0x10000000, g2=1 icctl g0,g1,g2 # Load and lock 1 block of cache # (one way) with # location of code at starting # 0x10000000. 65BH Opcode: icctl See Also: sysctl This instruction is implemented on the 80960Rx, 80960Hx and 80960Jx pro- Notes: cessor families only, and may or may not be implemented on future i960 pro- cessors.
Page 178: Intctl
INSTRUCTION SET REFERENCE 6.2.34 intctl Global Enable and Disable of Interrupts Mnemonic: intctl src1 Format: intctl reg/lit Description: Globally enables, disables or returns the current status of interrupts depending on the value of src1. Returns the previous interrupt enable state (1 for enabled or 0 for disabled) in dst.
Page 179 INSTRUCTION SET REFERENCE Faults: STANDARD Refer to section 6.1.6, “Faults” (pg. 6-5). TYPE.MISMATCH Attempt to execute instruction while not in supervisor mode. Example: # ICON.gie = 0, interrupts enabled intctl 0, g4 # Disable interrupts (ICON.gie = 1) # g4 = 1 658H Opcode: intctl...
Page 180: Intdis
INSTRUCTION SET REFERENCE 6.2.35 intdis Global Interrupt Disable Mnemonic: intdis Format: intdis Description: Globally disables interrupts and ensures that the change takes effect before the instruction completes. This operation is implemented by setting ICON.gie to one. if (PC.em != supervisor) Action: generate_fault(TYPE.MISMATCH);...
Page 181: Inten
INSTRUCTION SET REFERENCE 6.2.36 inten global interrupt enable Mnemonic: inten Format: inten Description: Globally enables interrupts and ensures that the change takes effect before the instruction completes. This operation is implemented by clearing ICON.gie to zero. if (PC.em != supervisor) Action: generate_fault(TYPE.MISMATCH);...
Page 182: Load
INSTRUCTION SET REFERENCE 6.2.37 LOAD Load Mnemonic: Load Ordinal Byte ldob Load Ordinal Short ldos Load Integer Byte ldib ldis Load Integer Short Load Long Load Triple Load Quad src, Format: Description: Copies byte or byte string from memory into a register or group of successive registers.
Page 183 INSTRUCTION SET REFERENCE ldib: dst[7:0] = read_memory(effective_address)[7:0]; if(dst[7] == 0) dst[31:8] = 0x000000; else dst[31:8] = 0xFFFFFF; ldos: dst = read_memory(effective_address)[15:0]; # Order depends on endianism. See section 2.2.2, “Byte Ordering” (pg. 2-4) dst[31:16] = 0x0000; if((effective_address[0] != 0 ) && unaligned_fault_enabled) generate_fault(OPERATION.UNALIGNED);...
Page 184 INSTRUCTION SET REFERENCE dst_+_2 = read_memory(effective_adddress_+_8)[31:0]; if((effective_address[3:0] != 0000 ) && unaligned_fault_enabled) generate_fault(OPERATION.UNALIGNED); ldq: if((reg_number(dst) % 4) != 0) generate_fault(OPERATION.INVALID_OPERAND); # dst not modified. else dst = read_memory(effective_adddress)[31:0]; # Order depends on endianism. # See section 2.2.2, “Byte Ordering” (pg. 2-4) dst_+_1 = read_memory(effective_adddress_+_4)[31:0];...
Page 185 INSTRUCTION SET REFERENCE 6.2.38 Load Address Mnemonic: src, Format: Description: Computes the effective address specified with src and stores it in dst. The src address is not checked for validity. Any addressing mode may be used to calculate efa. An important application of this instruction is to load a constant longer than 5 bits into a register.
Page 186: Mark
INSTRUCTION SET REFERENCE 6.2.39 mark Mark Mnemonic: mark Format: mark Description: Generates mark trace fault when mark trace mode is enabled. Mark trace mode is enabled when the PC register trace enable bit (bit 0) and the TC register mark trace mode bit (bit 7) are set. When mark trace mode is not enabled, behaves like a no-op.
Page 187: Modac
INSTRUCTION SET REFERENCE 6.2.40 modac Modify AC Mnemonic: modac mask, src, Format: modac reg/lit reg/lit Description: Reads and modifies the AC register. src contains the value to be placed in the AC register; mask specifies bits that may be changed. Only bits set in mask are modified.
Page 188: Modi
INSTRUCTION SET REFERENCE 6.2.41 modi Modulo Integer Mnemonic: modi src1, src2, Format: modi reg/lit reg/lit Description: Divides src2 by src1, where both are integers and stores the modulo remainder of the result in dst. When the result is nonzero, dst has the same sign as src1.
Page 189: Modify
INSTRUCTION SET REFERENCE 6.2.42 modify Modify Mnemonic: modify mask, src, src/dst Format: modify reg/lit reg/lit Description: Modifies selected bits in src/dst with bits from src. The mask operand selects the bits to be modified: only bits set in the mask operand are modified in src/dst.
Page 190: Modpc
INSTRUCTION SET REFERENCE 6.2.43 modpc Modify Process Controls Mnemonic: modpc src, mask, src/dst Format: modpc reg/lit reg/lit Description: Reads and modifies the PC register as specified with mask and src/dst. src/dst operand contains the value to be placed in the PC register; mask operand specifies bits that may be changed.
Page 191 INSTRUCTION SET REFERENCE See Also: modac, modtc Notes: Since modpc does not switch stacks, it should not be used to switch the mode of execution from supervisor to user (the supervisor stack can get corrupted in this case). The call and return mechanism should be used instead. 6-79...
Page 192: Modtc
INSTRUCTION SET REFERENCE 6.2.44 modtc Modify Trace Controls Mnemonic: modtc mask, src2, Format: modtc reg/lit reg/lit Description: Reads and modifies TC register as specified with mask and src2. The src2 operand contains the value to be placed in the TC register; mask operand specifies bits that may be changed.
Page 193: Move
INSTRUCTION SET REFERENCE 6.2.45 MOVE Move Mnemonic: Move Long movl Move Triple movt Move Quad movq Format: mov* src1, reg/lit Copies the contents of one or more source registers (specified with src) to one Description: or more destination registers (specified with dst). , src1 and dst specify the first (lowest numbered) movl movt...
Page 194 INSTRUCTION SET REFERENCE movt: if((reg_num(src1)%4 != 0) || (reg_num(dst)%4 != 0)) dst = undefined_value; dst_+_1 = undefined_value; dst_+_2 = undefined_value; generate_fault(OPERATION.INVALID_OPERAND); else if(is_reg(src1)) dst = src1; dst_+_1 = src1_+_1; dst_+_2 = src1_+_2; else dst[4:0] = src1; #src1 is a 5-bit literal. dst[31:5] = 0;...
Page 195 INSTRUCTION SET REFERENCE Opcode: 5CCH 5DCH movl 5ECH movt 5FCH movq See Also: LOAD, STORE, lda 6-83...
Page 196: Muli, Mulo
INSTRUCTION SET REFERENCE 6.2.46 muli, mulo Multiply Integer Mnemonic: muli Multiply Ordinal mulo src1, src2, Format: mul* reg/lit reg/lit Description: Multiplies the src2 value by the src1 value and stores the result in dst. The binary results from these two instructions are identical. The only difference is that muli can signal an integer overflow.
Page 197: Nand
INSTRUCTION SET REFERENCE 6.2.47 nand Nand Mnemonic: nand src1, src2, Format: nand reg/lit reg/lit Description: Performs a bitwise NAND operation on src2 and src1 values and stores the result in dst. dst = ~src2 | ~src1; Action: STANDARD Refer to section 6.1.6, “Faults”...
Page 198 INSTRUCTION SET REFERENCE 6.2.48 Mnemonic: src1, src2, Format: reg/lit reg/lit Description: Performs a bitwise NOR operation on the src2 and src1 values and stores the result in dst. dst = ~src2 & ~src1; Action: STANDARD Refer to section 6.1.6, “Faults” (pg. 6-5).
Page 199: Not, Notand
INSTRUCTION SET REFERENCE 6.2.49 not, notand Mnemonic: Not And notand src1, Format: reg/lit notand src1, src2, reg/lit reg/lit Performs a bitwise NOT ( instruction) or NOT AND ( instruction) Description: notand operation on the src2 and src1 values and stores the result in dst. Action: not: dst = ~src1;...
Page 200: Notbit
INSTRUCTION SET REFERENCE 6.2.50 notbit Not Bit Mnemonic: notbit bitpos, src2, Format: notbit reg/lit reg/lit Description: Copies the src2 value to dst with one bit toggled. The bitpos operand specifies the bit to be toggled. dst = src2 ^ 2**(src1%32); Action: STANDARD Refer to...
Page 201: Notor
INSTRUCTION SET REFERENCE 6.2.51 notor Not Or Mnemonic: notor src1, src2, Format: notor reg/lit reg/lit Description: Performs a bitwise NOTOR operation on src2 and src1 values and stores result in dst. dst = ~src2 | src1; Action: STANDARD Refer to section 6.1.6, “Faults”...
Page 202: Or, Ornot
INSTRUCTION SET REFERENCE 6.2.52 or, ornot Mnemonic: Or Not ornot src1, src2, Format: reg/lit reg/lit ornot src1, src2, reg/lit reg/lit Performs a bitwise OR ( instruction) or ORNOT ( instruction) Description: ornot operation on the src2 and src1 values and stores the result in dst. Action: dst = src2 | src1;...
Page 203: Remi, Remo
INSTRUCTION SET REFERENCE 6.2.53 remi, remo Remainder Integer Mnemonic: remi Remainder Ordinal remo src1, src2, Format: rem* reg/lit reg/lit Description: Divides src2 by src1 and stores the remainder in dst. The sign of the result (when nonzero) is the same as the sign of src2. Action: remi, remo: if(src1 == 0)
Page 204 INSTRUCTION SET REFERENCE 6.2.54 Return Mnemonic: Format: Description: Returns program control to the calling procedure. The current stack frame (i.e., that of the called procedure) is deallocated and the FP is changed to point to the calling procedure’s stack frame. Instruction execution is continued at the instruction pointed to by the RIP in the calling procedure’s stack frame, which is the instruction immediately following the call instruction.
Page 205 INSTRUCTION SET REFERENCE case 011 # supervisor return, trace on return enabled if(execution_mode != supervisor) get_FP_and_IP(); else PC.te = 1; execution_mode = user; get_FP_and_IP(); break; case 100 #reserved - unpredictable behavior break; case 101 #reserved - unpredictable behavior break; case 110 #reserved - unpredictable behavior break;...
Page 206: Rotate
INSTRUCTION SET REFERENCE 6.2.55 rotate Rotate Mnemonic: rotate len, src2, Format: rotate reg/lit reg/lit Description: Copies src2 to dst and rotates the bits in the resulting dst operand to the left (toward higher significance). Bits shifted off left end of word are inserted at right end of word.
Page 207: Scanbit
INSTRUCTION SET REFERENCE 6.2.56 scanbit Scan For Bit Mnemonic: scanbit src1, Format: scanbit reg/lit Description: Searches src1 for a set bit (1 bit). When a set bit is found, the bit number of the most significant set bit is stored in the dst and the condition code is set to .
Page 208: Scanbyte
INSTRUCTION SET REFERENCE 6.2.57 scanbyte Scan Byte Equal Mnemonic: scanbyte src1, src2 Format: scanbyte reg/lit reg/lit Description: Performs byte-by-byte comparison of src1 and src2 and sets condition code to 010 when any two corresponding bytes are equal. When no corresponding bytes are equal, condition code is set to 000 if((src1 &...
Page 209: Sel
INSTRUCTION SET REFERENCE 6.2.58 SEL<cc> Select Based on Unordered Mnemonic: selno Select Based on Greater selg Select Based on Equal sele Select Based on Greater or Equal selge sell Select Based on Less selne Select Based on Not Equal Select Based on Less or Equal selle Select Based on Ordered selo...
Page 210 INSTRUCTION SET REFERENCE Example: # AC.cc = 010 sele g0,g1,g2 # g2 = g1 # AC.cc = 001 sell g0,g1,g2 # g2 = g0 784H Opcode: selno 794H selg 7A4H sele selge 7B4H sell 7C4H selne 7D4H 7E4H selle 7F4H selo See Also: MOVE, TEST<cc>, cmpi, cmpo, SUB<cc>...
Page 211: Setbit
INSTRUCTION SET REFERENCE 6.2.59 setbit Set Bit Mnemonic: setbit bitpos, src, Format: setbit reg/lit reg/lit Description: Copies src value to dst with one bit set. bitpos specifies bit to be set. Action: dst = src | (2**(bitpos%32)); STANDARD Refer to section 6.1.6, “Faults”...
Page 212: Shift
INSTRUCTION SET REFERENCE 6.2.60 SHIFT Shift Left Ordinal Mnemonic: shlo Shift Right Ordinal shro Shift Left Integer shli Shift Right Integer shri shrdi Shift Right Dividing Integer Format: len, src, reg/lit reg/lit Shifts src left or right by the number of bits indicated with the len operand Description: and stores the result in dst.
Page 213 INSTRUCTION SET REFERENCE shli: if(len > 32) count = 32; else count = src1; temp = src; while((temp[31] == temp[30]) && (count > 0)) temp = (temp * 2)[31:0]; count = count - 1; dst = temp; if(count > 0) if(AC.om == 1) AC.of = 1;...
Page 214 INSTRUCTION SET REFERENCE See Also: divi, muli, rotate, eshro Notes: shli shrdi are identical to multiplications and divisions for all positive and negative values of src2. shri is the conventional arithmetic right shift that does not produce a correct quotient when src2 is negative. 6-102...
Page 215: Spanbit
INSTRUCTION SET REFERENCE 6.2.61 spanbit Span Over Bit Mnemonic: spanbit src, Format: spanbit reg/lit Description: Searches src value for the most significant clear bit (0 bit). When a most significant 0 bit is found, its bit number is stored in dst and condition code is set to 010 .
Page 216: Store
INSTRUCTION SET REFERENCE 6.2.62 STORE Store Mnemonic: Store Ordinal Byte stob Store Ordinal Short stos Store Integer Byte stib stis Store Integer Short Store Long Store Triple Store Quad src1, Format: Description: Copies a byte or group of bytes from a register or group of registers to memory.
Page 217 INSTRUCTION SET REFERENCE Action: stob: if (illegal_write_to_on_chip_RAM_or_MMR) generate_fault(TYPE.MISMATCH); else store_to_memory(effective_address)[7:0] = src1[7:0]; stib: if (illegal_write_to_on_chip_RAM_or_MMR) generate_fault(TYPE.MISMATCH); else if ((src1[31:8] != 0) && (src1[31:8] != 0xFFFFFF)) store_to_memory(effective_address)[7:0] = src1[7:0]; if (AC.om == 1) AC.of = 1; else generate_fault(ARITHMETIC.OVERFLOW); else store_to_memory(effective_address)[7:0] = src1[7:0]; end if;...
Page 218 INSTRUCTION SET REFERENCE else store_to_memory(effective_address)[15:0] = src1[15:0]; stl: if (illegal_write_to_on_chip_RAM_or_MMR) generate_fault(TYPE.MISMATCH); else if (reg_number(src1) % 2 != 0) generate_fault(OPERATION.INVALID_OPERAND); else if ((effective_address[2:0] != ) && unaligned_fault_enabled) store_to_memory(effective_address)[31:0] = src1; store_to_memory(effective_address + 4)[31:0] = src1_+_1; generate_fault (OPERATION.UNALIGNED); else store_to_memory(effective_address)[31:0] = src1; store_to_memory(effective_address + 4)[31:0] = src1_+_1;...
Page 219 INSTRUCTION SET REFERENCE store_to_memory(effective_address + 12)[31:0] = src1_+_3; generate_fault (OPERATION.UNALIGNED); else store_to_memory(effective_address)[31:0] = src1; store_to_memory(effective_address + 4)[31:0] = src1_+_1; store_to_memory(effective_address + 8)[31:0] = src1_+_2; store_to_memory(effective_address + 12)[31:0] = src1_+_3; STANDARD Refer to section 6.1.6, “Faults” (pg. 6-5). Faults: ARITHMETIC.OVERFLOW stib stis Example: st g2, 1254 (g6)
Page 220: Subc
INSTRUCTION SET REFERENCE 6.2.63 subc Subtract Ordinal With Carry Mnemonic: subc src1, src2, Format: subc reg/lit reg/lit Description: Subtracts src1 from src2, then subtracts the opposite of condition code bit 1 (used here as the carry bit) and stores the result in dst. When the ordinal subtraction results in a carry, condition code bit 1 is set to 1, otherwise it is set to 0.
Page 221: Sub
INSTRUCTION SET REFERENCE 6.2.64 SUB<cc> Subtract Ordinal if Unordered Mnemonic: subono Subtract Ordinal if Greater subog Subtract Ordinal if Equal suboe Subtract Ordinal if Greater or Equal suboge subol Subtract Ordinal if Less subone Subtract Ordinal if Not Equal Subtract Ordinal if Less or Equal subole Subtract Ordinal if Ordered suboo...
Page 222 INSTRUCTION SET REFERENCE Action: SUBO<cc>: if ((mask & AC.cc) || (mask == AC.cc)) (src2 - src1)[31:0]; SUBI<cc>: if ((mask & AC.cc) || (mask == AC.cc)) true_result = (src2 - src1); dst = true_result[31:0]; if((true_result > (2**31) - 1) || (true_result < -2**31)) # Check for overflow if (AC.om == 1) AC.of...
Page 223 INSTRUCTION SET REFERENCE See Also: subc, subi, subo, SEL<cc>, TEST<cc> Notes: These core instructions are not implemented on 80960Cx, Kx and Sx proces- sors. 6-111...
Page 224: Subi, Subo
INSTRUCTION SET REFERENCE 6.2.65 subi, subo Subtract Integer Mnemonic: subi Subtract Ordinal subo src1, src2, Format: sub* reg/lit reg/lit Description: Subtracts src1 from src2 and stores the result in dst. The binary results from these two instructions are identical. The only difference is that subi signal an integer overflow.
Page 225: Syncf
INSTRUCTION SET REFERENCE 6.2.66 syncf Synchronize Faults Mnemonic: syncf Format: syncf Description: Waits for all faults to be generated that are associated with any prior uncompleted instructions. if(AC.nif == 1) Action: break; else wait_until_all_previous_instructions_in_flow_have_completed(); This also means that all of the faults on these instructions have been reported.
Page 226: Figure 6-7. Src1 Operand Interpretation
INSTRUCTION SET REFERENCE 6.2.67 sysctl System Control Mnemonic: sysctl src1, src2, src/dst Format: sysctl reg/lit reg/lit Description: Performs system management and control operations including requesting software interrupts, invalidating the instruction cache, configuring the instruction cache, processor reinitialization, modifying memory-mapped registers, and acquiring breakpoint resource information. Processor control function specified by the message field of src1 is executed.
Page 227: Figure 6-8. Src/Dst Interpretation For Breakpoint Resource Request
INSTRUCTION SET REFERENCE Table 6-19. Cache Mode Configuration Mode Field Mode Description 80960JA 80960JF/JD 80960JT Normal cache enabled 2 Kbyte 4 Kbyte 16 Kbyte Full cache disabled 2 Kbyte 4 Kbyte 16 Kbyte Load and lock one way or 110 1 Kbyte 2 Kbyte 8 Kbyte...
Page 228 4,6: # Load & Lock code into I-Cache # All contiguous blocks are locked. # Note: block = way on i960 Jx processor. # src2 has starting address of code to lock. # src2 is aligned to a quad word # boundary.
Page 229 INSTRUCTION SET REFERENCE memory[control_reg_addr(i,grpoff)] = memory[i+grpoff]; break; case 5: # Modify One Memory-Mapped Control Register (MMR) Action: # src1[31:16] has lower 2 bytes of MMR address # src2 has value to write; dst has mask. # After operation, dst has old value of MMR addr = (0xff00 <<...
Page 230: Test
INSTRUCTION SET REFERENCE 6.2.68 TEST<cc> Test For Equal Mnemonic: teste Test For Not Equal testne Test For Less testl Test For Less Or Equal testle testg Test For Greater testge Test For Greater Or Equal Test For Ordered testo Test For Not Ordered testno dst:src1 Format:...
Page 231 INSTRUCTION SET REFERENCE Action: For all TEST<cc> except testno if((mask & AC.cc) != 000 src1 = 1; #true value else src1 = 0; #false value testno: if(AC.cc == 000 src1 = 1; #true value else src1 = 0; #false value Faults: STANDARD Refer to...
Page 232: Xnor, Xor
INSTRUCTION SET REFERENCE 6.2.69 xnor, xor Exclusive Nor Mnemonic: xnor Exclusive Or src1, src2, Format: xnor reg/lit reg/lit src1, src2, reg/lit reg/lit Performs a bitwise XNOR ( instruction) or XOR ( instruction) Description: xnor operation on the src2 and src1 values and stores the result in dst. Action: xnor: dst = ~(src2 | src1) | (src2 &...
Page 233 PROCEDURE CALLS...
Page 235 CHAPTER 7 PROCEDURE CALLS This chapter describes mechanisms for making procedure calls, which include branch-and-link instructions, built-in call and return mechanism, call instructions ( call callx calls ), return instruction ( ) and call actions caused by interrupts and faults. ®...
Page 236: Call And Return Mechanism
PROCEDURE CALLS The processor performs two call actions: local When a local call is made, execution mode remains unchanged and the stack frame for the called procedure is placed on the local stack. The local stack refers to the stack of the calling procedure. supervisor When a supervisor call is made from user mode, execution mode is switched to supervisor and the stack frame for the called procedure is placed on the...
Page 237: Figure 7-1. Procedure Stack Structure And Local Registers
PROCEDURE CALLS The procedure stack can be located anywhere in the address space and grows from low addresses to high addresses. It consists of contiguous frames, one frame for each active procedure. Local registers for a procedure are assigned a save area in each stack frame (Figure 7-1).
Page 238: Local Register And Stack Management
SALIGN parameter (see section A.3, “Data and Data Structure Alignment” (pg. A-3)). In the i960 Jx processor, stacks are aligned on 16-byte boundaries (see Figure 7-1). When the processor needs to create a new frame on a procedure call, it adds a padding area to the stack so that the new frame starts on a 16-byte boundary.
Page 239: Considerations When Popping Data Off The Stack
PROCEDURE CALLS 7.1.2.4 Considerations When Popping Data off the Stack Care should be taken in reading the stack in the presence of unforeseen faults and interrupts. In the general case, to ensure that data about to be popped off the stack is not corrupted by a fault or interrupt record, the data should be read first and then the sp should be decremented: subo 24,sp,r4...
Page 240: Call Operation
PROCEDURE CALLS The events for call and return operations are given in a logical order of operation. The i960 Jx processor can execute independent operations in parallel; therefore, many of these events execute simultaneously. For example, to improve performance, the processor often begins prefetching of the target instruction for the call or return before the operation is complete.
Page 241: Return Operation
PROCEDURE CALLS 7.1.3.2 Return Operation A return from any call type — explicit or implicit — is always initiated with a return ( instruction. On a return, the processor performs these operations: The current stack frame and local registers are deallocated by loading the FP register with the value of the PFP register.
Page 242: Reserving Local Register Sets For High Priority Interrupts
PROCEDURE CALLS For most programs, the existence of the multiple local register sets and their saving/restoring in the stack frames should be transparent. However, there are some special cases: • A store to the register save area in memory does not necessarily update a local register set, unless user software executes first.
Page 243: Figure 7-2. Frame Spill
PROCEDURE CALLS call with no frame spill call with frame spill Procedure Stack (0 = Main, successive numbers indicate nested procedure level) local register set n stored Frame on procedure stack Spill user stack space reserved for local register set n Local Register Cache (with no sets reserved for high priority interrupts)
Page 244: Figure 7-3. Frame Fill
PROCEDURE CALLS return with no frame fill return with frame fill Procedure Stack (0 = Main, successive numbers indicate nested procedure level) Frame Fill Local Register Cache (With no sets reserved Empty Empty Empty for high priority interrupts) Empty Empty Empty Empty Empty...
Page 245: Mapping Local Registers To The Procedure Stack
PROCEDURE CALLS 7.1.5 Mapping Local Registers to the Procedure Stack Each local register set is mapped to a register save area of its respective frame in the procedure stack (Figure 7-1). Saved local register sets are frequently cached on-chip rather than saved to memory.
Page 246: Parameter Passing
PROCEDURE CALLS Example 7-1. flushreg # Do a context switch. # Assume PFP = 0x5000. flushreg # Flush Frames to correct address. lda 0x8000,pfp flushreg # Ensure that "ret" gets updated PFP. flushreg before the modification is necessary to ensure that the frame of the previous context (mapped to 0x5000 in the example) is “spilled”...
Page 247 PROCEDURE CALLS The argument list can be stored anywhere in memory; however, a convenient place to store an argument list is in the stack for a calling procedure. Space for the argument list is created by incre- menting the SP register value. When the argument list is stored in the current stack, the argument list is automatically deallocated when no longer needed.
Page 248: Local Calls
PROCEDURE CALLS Example 7-2. Parameter Passing Code Example # Example of parameter passing . . . # C-source:int a,b[10]; a = proc1(a,1,’x’,&b[0]); assembles to ... r3,g0 # value of a ldconst 1,g1 # value of 1 ldconst 120,g2 # value of “x” 0x40(fp),g3 # reference to b[10] call...
Page 249: System Calls
PROCEDURE CALLS SYSTEM CALLS A system call is a call made via the system procedure table. It can be used to make a system-local call — similar to a local call made with in the sense that there is no stack nor mode call callx switch —...
Page 250: Figure 7-4. System Procedure Table
PROCEDURE CALLS 000H 008H supervisor stack pointer base 00CH 010H Trace Control 02CH 030H procedure entry 0 034H procedure entry 1 procedure entry 2 038H 03CH 438H 43CH procedure entry 259 Procedure Entry address Reserved Entry Type: (Initialize to 0) 00 - Local 10-Supervisor Preserved...
Page 251: Procedure Entries
PROCEDURE CALLS 7.5.1.1 Procedure Entries A procedure entry in the system procedure table specifies a procedure’s location and type. Each entry is one word in length and consists of an address (IP) field and a type field. The address field gives the address of the first instruction of the target procedure.
Page 252: System Call To A Local Procedure
PROCEDURE CALLS 7.5.2 System Call to a Local Procedure When a instruction references an entry in the system procedure table with an entry type of calls 00, the processor executes a system-local call to the selected procedure. The action that the processor performs is the same as described in section 7.1.3.1, “Call Operation”...
Page 253: User And Supervisor Stacks
PROCEDURE CALLS USER AND SUPERVISOR STACKS When using the user-supervisor protection mechanism, the processor maintains separate stacks in the address space. One of these stacks — the user stack — is for procedures executed in user mode; the other stack — the supervisor stack — is for procedures executed in supervisor mode. The user and supervisor stacks are identical in structure (Figure 7-1).
Page 254: Returns
PROCEDURE CALLS RETURNS The return ( ) instruction provides a generalized return mechanism that can be used to return from any procedure that was entered by , an interrupt call or a fault call. When call calls callx executes, the processor uses the information from the return-type field in the PFP register (Figure 7-5) to determine the type of return action to take.
Page 255: Branch-And-Link
PROCEDURE CALLS Table 7-2. Encoding of Return Status Field Return Status Call Type Return Action Field Local call (system-local call or Local return system-supervisor call made from (return to local stack; no mode switch) supervisor mode) Fault call Fault return Supervisor return (return to user stack, mode switch to user System-supervisor from user...
Page 257 FAULTS...
Page 259: Fault Handling Overview
CHAPTER 8 FAULTS ® This chapter describes the i960 Jx processor’s fault handling facilities. Subjects covered include the fault handling data structures and fault handling mechanisms. See section 8.10, “FAULT REFERENCE” (pg. 8-21) for detailed information on each fault type. FAULT HANDLING OVERVIEW The i960 processor architecture defines various conditions in code and/or the processor’s internal state that could cause the processor to deliver incorrect or inappropriate results or that could cause...
Page 260 FAULTS The fault table contains pointers to fault handling procedures. The system procedure table optionally provides an interface to any fault handling procedure and allows faults to be handled in supervisor mode. Stack frames for fault handling procedures are created on either the user or supervisor stack, depending on the mode in which the fault is handled.
Page 261: Fault Types
It then uses the type number to select the fault handling procedure. The fault handling procedure can optionally use the subtype number to select a specific fault handling action. The i960 Jx processor recognizes i960 architecture-defined faults and a new fault subtype for detecting unaligned memory accesses. Table 8-1 lists all faults that the i960 Jx processor detects, arranged by type and subtype.
Page 262: Fault Table
FAULTS Table 8-1: • The first (left-most) column contains the fault type numbers in hexadecimal. • The second column shows the fault type name. • The third column gives the fault subtype number as either: (1) a hexadecimal number or (2) as a bit position in the fault record’s 8-bit fault subtype field.
Page 263: Figure 8-2. Fault Table And Fault Table Entries
FAULTS Fault Table PARALLEL/OVERRIDE Fault Entry TRACE Fault Entry OPERATION Fault Entry ARITHMETIC Fault Entry CONSTRAINT Fault Entry PROTECTION Fault Entry TYPE Fault Entry Local-Call Entry Fault-Handler Procedure Address System-Call Entry Fault-Handler Procedure Number 0000 027FH Reserved (Initialize to 0) Figure 8-2.
Page 264: Stack Used In Fault Handling
FAULTS As indicated in Figure 8-2, two fault table entry types are allowed: local-call entry and system-call entry. Each is two words in length. The entry type field (bits 0 and 1 of the entry’s first word) and the value in the entry’s second word determine the entry type. local-call entry Provides an instruction pointer for the fault handling procedure.
Page 265: Fault Record Description
FAULTS 8.5.1 Fault Record Description Figure 8-3 shows the fault record’s structure. In this record, the fault’s type number and subtype number (or bit positions for multiple subtypes) are stored in the fault type and subtype fields, respectively. The Address of Faulting Instruction Field contains the IP of the instruction that caused the processor to fault.
Page 266: Fault Record Location
FAULTS The Resumption Information Field is used to store information about a pending trace fault. If a trace fault and a non-trace fault occur simultaneously, the non-trace fault is serviced first and the pending trace may be lost depending on the non-trace fault encountered. The Trace Reporting paragraph for each fault specifies whether the pending trace is kept or lost.
Page 267: Multiple And Parallel Faults
1. 8.6.4 Parallel Faults The i960 Jx processor exploits the architecture’s tolerance of out-of-order instruction execution by issuing instructions to independent execution units on the chip. The following subsections describe how the processor handles faults in this environment.
Page 268: Faults On Multiple Instructions Executed In Parallel
On the i960 Jx processor, the overflow fault is the only fault that can happen with a delay. muli...
Page 269: Fault Record For Parallel Faults
To calculate byte offsets, “n” indicates the fault number. Thus, for the second fault recorded (n=2), the relationship (NFP-4-(n * 32)) reduces to NFP-72. For the i960 Jx processor, a maximum of two faults are reported in the parallel fault record, and one of them must be the ARITHMETIC.INTEGER_OVERFLOW fault on a...
Page 270: System Error
FAULTS A fault that occurs during any of the above actions is called an override fault. In response to this condition, the processor does the following: • Switches the execution mode to supervisor. • Selects the override condition that shows that the writing of the fault record was unsuccessful. If no such fault exists, the processor selects one of the other fault conditions.
Page 271: Possible Fault Handling Procedure Actions
FAULTS 8.7.1 Possible Fault Handling Procedure Actions The processor allows easy recovery from many faults that occur. When fault recovery is possible, the processor’s fault handling mechanism allows the processor to automatically resume work on the program or pending interrupt when the fault occurred. Resumption is initiated with a instruction in the fault handling procedure.
Page 272: Faults Happening During Instruction Execution
FAULTS 8.7.2.2 Faults Happening During Instruction Execution The following fault types occur during instruction execution: • CONSTRAINT.RANGE • OPERATION.UNALIGNED • ARITHMETIC.INTEGER_OVERFLOW For these faults, the fault handler must explicitly modify the RIP to return to the faulting application (except for ARITHMETIC.INTEGER_OVERFLOW). When a fault occurs during or after execution of the faulting instruction, the fault may be accompanied by a program state change such that program execution cannot be resumed after the fault is handled.
Page 273: Returning To The Point In The Program Where The Fault Occurred
FAULTS 8.7.4 Returning to the Point in the Program Where the Fault Occurred As described in section 8.7.2, “Program Resumption Following a Fault” (pg. 8-13), most faults can be handled such that program control flow is not affected. In this case, the processor allows a program to be resumed at the point where the fault occurred, following a return from a fault handling procedure (initiated with a instruction).
Page 274: Fault Handling Action
FAULTS TC register trace mode bits and the PC register trace enable bit support trace faults. Trace mode bits enable trace modes; the trace enable bit (PC.te) enables trace fault generation. The use of these bits is described in the trace faults description in section 8.10, “FAULT REFERENCE”...
Page 275: Local Fault Call
FAULTS 8.8.1 Local Fault Call When the selected fault handler entry in the fault table is an entry type 000 (a local procedure), the processor operates as described in section 7.1.3.1, “Call Operation” (pg. 7-6), with the following exceptions: • A new frame is created on the stack that the processor is currently using.
Page 276: Faults And Interrupts
FAULTS • The fault record is copied into the area allocated for it in the new stack frame, beginning at NFP-1. (See Figure 8-4.) • The processor gets the IP for the first instruction of the fault handling procedure from the system procedure table (using the index provided in the fault table entry).
Page 277: Precise And Imprecise Faults
FAULTS PRECISE AND IMPRECISE FAULTS As described in section 8.10.5, “PARALLEL Faults” (pg. 8-27), the i960 architecture — to support parallel and out-of-order instruction execution — allows some faults to be generated together. The processor provides two mechanisms for controlling the circumstances under which faults are generated: the AC register no-imprecise-faults bit (AC.nif) and the instructions that synchronize faults.
Page 278: No Imprecise Faults (Ac.nif) Bit
FAULTS 8.9.4 No Imprecise Faults (AC.nif) Bit The Arithmetic Controls no imprecise faults (AC.nif) bit controls imprecise fault generation. If AC.nif is set, out of order instruction execution is disabled and all faults generated are precise. Therefore, setting this bit will reduce processor performance. If AC.nif is clear, several imprecise faults may be reported together in a parallel fault record.
Page 279: Fault Reference
FAULTS 8.10 FAULT REFERENCE This section describes each fault type and subtype and gives detailed information about what is stored in the various fields of the fault record. The section is organized alphabetically by fault type. The following paragraphs describe the information that is provided for each fault type. Fault Type: Gives the number that appears in the fault record fault-type field when the fault is generated.
Page 280: Arithmetic Faults
FAULTS 8.10.1 ARITHMETIC Faults Fault Type: Number Name Fault Subtype: Reserved INTEGER_OVERFLOW ZERO_DIVIDE 3H-FH Reserved Indicates a problem with an operand or the result of an arithmetic Function: instruction. An INTEGER_OVERFLOW fault is generated when the result of an integer instruction overflows its destination and the AC register integer overflow mask is cleared.
Page 281: Constraint Faults
FAULTS 8.10.2 CONSTRAINT Faults Fault Type: Number Name Fault Subtype: Reserved RANGE 2H-FH Reserved Indicates the program or procedure violated an architectural constraint. Function: A CONSTRAINT.RANGE fault is generated when a FAULT<cc> instruction is executed and the AC register condition code field matches the condition required by the instruction.
Page 282: Operation Faults
FAULTS 8.10.3 OPERATION Faults Fault Type: Number Name Fault Subtype: Reserved INVALID_OPCODE UNIMPLEMENTED UNALIGNED INVALID_OPERAND 5H - FH Reserved Indicates the processor cannot execute the current instruction Function: because of invalid instruction syntax or operand semantics. An INVALID_OPCODE fault is generated when the processor attempts to execute an instruction containing an undefined opcode or addressing mode.
Page 283 FAULTS Class: Imprecise. For the INVALID_OPCODE and UNIMPLEMENTED faults (case: Program State Changes: store to MMR), the destination of the faulting instruction is not modified. (For the UNALIGNED fault, the memory operation completes correctly before the fault is reported.) In all other cases, the destination is undefined.
Page 284: Override Faults
FAULTS 8.10.4 OVERRIDE Faults Fault table entry = 0H Fault Type: The fault type in the fault record on the stack equals the fault type of the initial fault. Fault Subtype: The fault subtype in the fault record on the stack equals the fault subtype of the initial fault.
Page 285: Parallel Faults
FAULTS 8.10.5 PARALLEL Faults Fault table entry = 0H Fault Type: Fault type in fault record = fault type of one of the parallel faults. Fault subtype of one of the parallel faults. Fault Subtype: Fault OType: Fault OSubtype: Number of parallel faults. section 8.6.4, “Parallel Faults”...
Page 286: Protection Faults
FAULTS 8.10.6 PROTECTION Faults Fault Type: Number Name Fault Subtype: Bit 0 Reserved Bit 1 LENGTH Bits 2-7 Reserved Indicates that a program or procedure is attempting to perform an Function: illegal operation that the architecture protects against. A PROTECTION.LENGTH fault is generated when the index operand used in a calls instruction points to an entry beyond the...
Page 287: Trace Faults
FAULTS 8.10.7 TRACE Faults Fault Type: Number Name Fault Subtype: Bit 0 Reserved Bit 1 INSTRUCTION Bit 2 BRANCH Bit 3 CALL Bit 4 RETURN Bit 5 PRERETURN Bit 6 SUPERVISOR Bit 7 MARK/BREAKPOINT Function: Indicates the processor detected one or more trace events. The event tracing mechanism is described in CHAPTER 9, TRACING AND DEBUGGING.
Page 288 FAULTS PRERETURN Generates a trace event prior to any instruction, provided the PFP register prereturn trace flag is set (the processor sets the flag automatically when a call trace is serviced). A prereturn trace fault is always generated alone. SUPERVISOR Generates a trace event following any instruction that references a calls...
Page 289 FAULTS RIP: Instruction immediately following the instruction traced, in instruction issue order, except PRERETURN. PRERETURN, the RIP is the return instruction traced. IP of the faulting instruction for all except prereturn trace and call Fault IP: trace (on implicit fault calls), for which the fault IP field is undefined.
Page 290: Type Faults
A TYPE.MISMATCH fault is generated when attempts are made to: • Execute a privileged (supervisor-mode only) instruction while the processor is in user mode. Privileged instructions on the i960 Jx processor are: modpc dcctl halt intctl...
Page 291 TRACING AND DEBUGGING...
Page 293: Trace Controls
The i960 Jx processor also provides four hardware breakpoint registers that generate trace events and trace faults. Two registers are dedicated to trapping on instruction execution addresses (IPB0,1), while the remaining two registers can trap on the addresses of various types of data accesses (DAB0,1).
Page 294: Figure 9-1. 80960Jx Trace Controls (Tc) Register
When the program is not in a trace fault handler, or when the trace is not for breakpoints, the TC event bits are clear. On the i960 Jx processor, TC register bits 0, 8 through 23 and 28 through 31...
Page 295: Pc Trace Enable Bit And Trace-Fault-Pending Flag
TRACING AND DEBUGGING 9.1.2 PC Trace Enable Bit and Trace-Fault-Pending Flag The Process Controls (PC) register trace enable bit and the trace-fault-pending flag in the PC field of the fault record control tracing (see section 3.7.3, “Process Controls (PC) Register” (pg. 3-21)).
Page 296: Branch Trace
TRACING AND DEBUGGING 9.2.2 Branch Trace When the branch-trace mode is enabled in TC (TC.b = 1) and PC.te is set, the processor generates a branch-trace fault immediately after a branch instruction executes, if the branch is taken. A branch-trace event is not generated for conditional-branch instructions that do not branch, branch-and-link instructions, and call-and-return instructions.
Page 297: Supervisor Trace
The hardware breakpoint registers are provided to enable generation of trace faults on instruction execution and data access. The i960 Jx processor implements two instruction and two data address breakpoint registers, denoted IPB0, IPB1, DAB0 and DAB1. The instruction and data address breakpoint registers are 32-bit registers.
Page 298: Requesting Modification Rights To Hardware Breakpoint Resources
TRACING AND DEBUGGING Hardware breakpoint registers may be armed or disarmed. When the registers are armed, hardware breakpoints can generate an architectural trace fault. When the registers are disarmed, no action occurs, and execution continues normally. Since instructions are always word aligned, the two low-order bits of the IPBx registers act as control bits.
Page 299: Breakpoint Control Register
If the value returned is zero, the application has not gained the rights to the breakpoint resources. Because the i960 Jx processor does not initialize the breakpoint registers from the control table during initialization (as i960 Cx processors do), the application must explicitly initialize the breakpoint registers in order to use them once modification rights have been granted by the instruction.
Page 300: Figure 9-2. Breakpoint Control Register (Bpcon)
TRACING AND DEBUGGING DAB0 DAB1 Hardware Reset Value: 0000 0000H Reserved Software Re-Init Value: 0000 0000H (Initialize to 0) Figure 9-2. Breakpoint Control Register (BPCON) Programming the BPCON register is summarized in Table 9-2 Table 9-3. Table 9-2. Configuring the Data Address Breakpoint (DAB) Registers PC.te DABx.e1 DABx.e0 Description...
Page 301: Data Address Breakpoint (Dab) Registers
TRACING AND DEBUGGING 9.2.7.5 Data Address Breakpoint (DAB) Registers The format for the Data Address Breakpoint (DAB) registers is shown in Figure 9-3. Each breakpoint register contains a 32-bit address of a byte to match on. A breakpoint is triggered when both a data access’s type and address matches that specified by BPCON and the appropriate DAB register.
Page 302: Figure 9-3. Data Address Breakpoint (Dab) Register Format
Figure 9-4. Instruction Breakpoint (IPB) Register Format Programming the instruction breakpoint register modes is shown in Table 9-4 On the i960 Jx processor, the instruction breakpoint memory-mapped registers can be read by using sysctl instruction only. They can be modified by sysctl or by a word-length store instruction.
Page 303: Generating A Trace Fault
TRACING AND DEBUGGING Table 9-4. Instruction Breakpoint Modes PC.te IPBx.m1 IPBx.m0 Action No action. Globally disabled. No action. IPBx disabled. Reserved. Reserved. Generate a Trace Fault. NOTE: “X” = don’t care. Reserved combinations must not be used. GENERATING A TRACE FAULT To summarize the information presented in the previous sections, the processor services a trace fault when PC.te is set and the processor detects any of the following conditions: •...
Page 304: Trace Fault Handling Procedure
TRACING AND DEBUGGING TRACE FAULT HANDLING PROCEDURE The processor calls the trace fault handling procedure when it detects a trace event. See section 8.7, “FAULT HANDLING PROCEDURES” (pg. 8-12) for general requirements for fault handling procedures. The trace fault handling procedure is involved in a specific way and is handled differently than other faults.
Page 305: Table 9-5. Tracing On Explicit Call
TRACING AND DEBUGGING 9.5.2.1 Tracing on Explicit Call Tracing an explicit call happens before execution of the first instruction of the procedure called. Tracing is not modified by using a instruction. Further, tracing is not modified by call callx using a instruction from supervisor mode.
Page 306: Table 9-6. Tracing On Implicit Call
(tracing is disabled on the way to a trace fault handler). On the i960 Jx processor, the parallel/override fault handler must be accessed through a system-supervisor call. Tracing is disabled on the way to the parallel/override fault handler.
Page 307: Tracing On Return From Implicit Call: Fault Case
TRACING AND DEBUGGING 9.5.2.3 Tracing on Return from Explicit Call Table 9-7 shows all cases. Table 9-7. Tracing on Return from Explicit Call PFP.rt2:0 Execution Mode PC.em Trace Enable Used for Trace on Return user or supervisor PC.te user PC.te super (from PFP.r[2:0]) Refer to...
Page 308: Tracing On Return From Implicit Call: Interrupt Case
Upon return from the interrupt, the trace fault is serviced if the interrupt handler did not switch to user mode. On the i960 Jx processor, the interrupt handler returns directly to the trace fault handler.
Page 309 TIMERS...
Page 311: Figure 10-1. Timer Functional Diagram
CHAPTER 10 TIMERS ® This chapter describes the i960 Jx processor’s dual, independent 32-bit timers. Topics include timer registers (TMRx, TCRx and TRRx), timer operation, timer interrupts, and timer register values at initialization. Each timer is programmed by the timer registers. These registers are memory-mapped within the processor, addressable on 32-bit boundaries.
Page 312: Table 10-1. Timer Performance Ranges
TIMERS Table 10-1. Timer Performance Ranges Bus Frequency (MHz) Max Resolution (ns) Max Range (mins) 14.3 30.3 17.4 22.9 28.6 62.5 35.8 10.1 TIMER REGISTERS As shown in Table 10-2, each timer has three memory-mapped registers: • Timer Mode Register - programs the specific mode of operation or indicates the current programmed status of the timer.
Page 313: Timer Mode Registers (Tmr0, Tmr1)
TIMERS 10.1.1 Timer Mode Registers (TMR0, TMR1) The Timer Mode Register (TMRx) lets the user program the mode of operation and determine the current status of the timer. TMRx bits are described in the subsections following Figure 10-2 are summarized in Table 10-4.
Page 314: Bit 0 - Terminal Count Status Bit (Tmrx.tc)
TIMERS 10.1.1.1 Bit 0 - Terminal Count Status Bit (TMRx.tc) The TMRx.tc bit is set when the Timer Count Register (TCRx) decrements to 0 and bit 2 (TMRx.reload) is not set for a timer. The TMRx.tc bit allows applications to monitor timer status through software instead of interrupts.
Page 315: Bit 2 - Timer Auto Reload Enable (Tmrx.reload)
TIMERS 10.1.1.3 Bit 2 - Timer Auto Reload Enable (TMRx.reload) The TMRx.reload bit determines whether the timer runs continuously or in single-shot mode. When TCRx = 0 and TMRx.enable = 1 and: TMRx.reload = 1 The timer runs continuously. The processor: Automatically loads TCRx with the value in the Timer Reload Register (TRRx), when TCRx value decrements to 0.
Page 316: Bits 4, 5 - Timer Input Clock Select (Tmrx.csel1:0)
TIMERS 10.1.1.5 Bits 4, 5 - Timer Input Clock Select (TMRx.csel1:0) User software programs the TMRx.csel bits to select the Timer Clock (TCLOCK) frequency. See Table 10-3. As shown in Figure 10-1, the bus clock is an input to the timer clock unit. These bits allow the application to specify whether TCLOCK runs at or slower than the bus clock frequency.
Page 317: Timer Reload Register (Trr0, Trr1)
TIMERS 10.1.3 Timer Reload Register (TRR0, TRR1) The Timer Reload Register (TRRx; Figure 10-4) is a 32-bit register that contains the timer’s reload count. The timer loads the reload count value into TCRx when TMRx.reload is set (1), TMRx.enable is set (1) and TCRx equals zero. As with TCRx, the valid programmable range is from 1H to FFFF FFFFH.
Page 318: Table 10-4. Timer Mode Register Control Bit Summary
TIMERS Software can read or write the TCRx value whether the timer is running or stopped. This lets the user monitor the count without using hardware interrupts. The TMRx.sup bit lets the programmer allow or prevent user mode writes to TCRx, TMRx and TRRx. When the TCRx value decrements to zero, the unit’s interrupt request signals the processor’s interrupt controller.
Page 319: Load/Store Access Latency For Timer Registers
TIMERS 10.2.2 Load/Store Access Latency for Timer Registers As with all other load accesses from internal memory-mapped registers, a load instruction that accesses a timer register has a latency of one internal processor cycle. With one exception, a store access to a timer register completes and all state changes take effect before the next instruction begins execution.
Page 320 TIMERS (Sheet 2 of 2) Table 10-5. Timer Responses to Register Bit Settings Name Status Action Bit is available 1 bus clock after executing a read instruction from (TMRx.sup) READ TMRx. Timer Register Supervisor Writing a ‘1’ locks out user mode writes within 1 bus clock after the Write Control WRITE store instruction executes to TMRx.
Page 321: Timer Interrupts
TIMERS 10.3 TIMER INTERRUPTS Each timer is the source for one interrupt. When a timer detects a zero count in its TCRx, the timer generates an internal edge-detected Timer Interrupt signal (TINTx) to the interrupt controller, and the interrupt-pending (IPND.tipx) bit is set in the interrupt controller. Each timer interrupt can be selectively masked in the Interrupt Mask (IMSK) register or handled as a dedicated hardware-requested interrupt.
Page 322: Uncommon Tcrx And Trrx Conditions
TIMERS 10.5 UNCOMMON TCRX AND TRRX CONDITIONS Table 10-4 summarizes the most common settings for programming the timer registers. Under certain conditions, however, it may be useful to set the Timer Count Register or the Timer Reload Register to zero before enabling the timer. Table 10-7 details the conditions and results when these conditions are set.
Page 323: Timer State Diagram
TIMERS 10.6 TIMER STATE DIAGRAM Figure 10-5 shows the common states of the Timer Unit. For uncommon conditions see section 10.5, “UNCOMMON TCRX AND TRRX CONDITIONS” (pg. 10-12). Hardware/Software Reset TMRx.enable = 0 TMRx.reload = 0 TMRx.sup = 0 TMRx.csel1:0 = 0 IPND.tip = 0 SW Write Bus Clock or...
Page 325 INTERRUPTS...
Page 327: Overview
For interrupt handler portability across the i960 processor family, the architecture defines a consistent interrupt state and interrupt-priority-handling mechanism. To manage and prioritize interrupt requests in parallel with processor execution, the i960 Jx processor provides an on-chip programmable interrupt controller.
Page 328: The I960 ® Jx Processor Interrupt Controller
The i960 Jx Processor Interrupt Controller The i960 Jx processor Interrupt Controller Unit (ICU) provides a flexible, low-latency means for requesting and posting interrupts and minimizing the core’s interrupt handling burden. Acting independently from the core, the interrupt controller posts interrupts requested by hardware and software sources and compares the priorities of posted interrupts with the current process priority.
Page 329: Software Requirements For Interrupt Handling
Priority-31 interrupts are handled as a special case. Even when the processor is executing at priority level 31, a priority-31 interrupt interrupts the processor. On the i960 Jx processor, the non-maskable interrupt (NMI) interrupts priority-31 execution; no interrupt can interrupt an NMI handler.
Page 330: Figure 11-2. Interrupt Table
INTERRUPTS 11.4 INTERRUPT TABLE The interrupt table (see Figure 11-2) is 1028 bytes in length and can be located anywhere in the non-reserved address space. It must be aligned on a word boundary. The processor reads a pointer to the interrupt table byte 0 during initialization. The interrupt table must be located in RAM since the processor must be able to read and write the table’s pending interrupt section.
Page 331: Vector Entries
0. Bits 0 and 1 of an entry indicate entry type: on the i960 Jx processor, only type 00 is valid. The other possible entry types are reserved and must not be used.
Page 332: Caching Portions Of The Interrupt Table
The purpose of caching these fields is to reduce interrupt latency by allowing the processor to access certain interrupt vector numbers and the pending interrupt information without having to make external memory accesses. The i960 Jx processor caches the following: •...
Page 333: Interrupt Stack And Interrupt Record
NFP-16. In the i960 Jx processor, the stack is aligned to a 16-byte boundary. When the processor needs to create a new frame on an interrupt call, it adds a padding area to the stack so that the new frame starts on a 16-byte boundary.
Page 334: Managing Interrupt Requests
The archi- tecture, however, leaves the interrupt request management strategy to the specific i960 processor family implementations. In the i960 Jx processor, a programmable on-chip interrupt controller manages all interrupt requests (Figure 11-12).
Page 335: Software Interrupts
External Interrupts: interrupts posted through the interrupt table, by an external agent to the i960 Jx processor. • Hardware interrupts: interrupts posted directly to the i960 Jx processor through an imple- mentation-dependent mechanism that may avoid using the interrupt table. 11.6.5.1...
Page 336 INTERRUPTS Example 11-1. Using sysctl to Request an Interrupt ldconst 0x53,g5 # Vector number 53H is loaded # into byte 0 of register g5 and # the value is zero extended into # byte 1 of the register sysctl g5, g5, g5 # Vector number 53H is posted A literal can be used to post an interrupt with a vector number from 8 to 31.
Page 337: Posting Software Interrupts Directly In The Interrupt Table
INTERRUPTS 11.6.5.2 Posting Software Interrupts Directly in the Interrupt Table Software can post interrupts by setting the desired pending-interrupt and pending-priorities bits directly. Direct posting requires that software ensure that no external I/O agents post a pending interrupt simultaneously, and that an interrupt cannot occur after one bit is set but before the other is set.
Page 338: Sampling Pending Interrupts In The Interrupt Table
At specific points, the processor checks the interrupt table for pending interrupts. If one is found, it is handled as if the interrupt occurred at that time. In the i960 Jx processor, a check for pending interrupts in the interrupt table is made when requesting a software interrupt with...
Page 339 INTERRUPTS Example 11-4. Sampling Pending Interrupts Check_For_Pending_Interrupts: x = read(pending_priorities); if(x == 0) return(); #nothing to do y = most_significant_bit(x); if(y != 31 && y <= current_priority) return(); x = atomic_read(pending_priorities); #synchronize if(x == 0) {atomic_write(pending_priorities) = x; return();} #interrupts disappeared # (e.g., handled by another processor) y = most_significant_bit(x);...
Page 340: Interrupt Controller Modes
INTERRUPTS 11.6.8 Interrupt Controller Modes The eight external interrupt pins can be configured for one of three modes: dedicated, expanded or mixed. Each mode is described in the subsections that follow. 11.6.8.1 Dedicated Mode In dedicated mode, each external interrupt pin is assigned a vector number. Vector numbers that may be assigned to a pin are those with the encoding PPPP 0010 (Figure 11-4), where bits...
Page 341: Figure 11-5. Expanded Mode
INTERRUPTS 11.6.8.2 Expanded Mode In expanded mode, up to 240 interrupts can be requested from external sources. Multiple external sources are externally encoded into the 8-bit interrupt vector number. This vector number is then applied to the external interrupt pins (Figure 11-5), with the XINT0 pin representing the least-significant bit and XINT7 the most significant bit of the number.
Page 342: Figure 11-6. Implementation Of Expanded Mode Sources
INTERRUPTS Enable Input Priority Priority Encoder Encoder Interrupt Sources up to 63 lines Priority ® To i960 Encoder processor’s INT pins Priority Encoder Figure 11-6. Implementation of Expanded Mode Sources 11-16...
Page 343: Mixed Mode
INTERRUPTS 11.6.8.3 Mixed Mode In mixed mode, pins XINT0 through XINT4 are configured for expanded mode. These pins are encoded for the five most-significant bits of an expanded-mode vector number; the three least-significant bits of the vector number are set internally to 010 .
Page 344: External Interface Description
11.7 EXTERNAL INTERFACE DESCRIPTION This section describes the physical characteristics of the interrupt inputs. The i960 Jx processor provides eight external interrupt pins and one non-maskable interrupt pin for detecting external interrupt requests. The eight external pins can be configured as dedicated inputs, where each pin is capable of requesting a single interrupt.
Page 345: Interrupt Detection Options
INTERRUPTS 11.7.2 Interrupt Detection Options The XINT[7:0] pins can be programmed for level-low or falling-edge detection when used as dedicated inputs. All dedicated inputs plus the NMI pin are programmed (globally) for fast sampling or debounce sampling. Expanded-mode inputs are always sampled in debounce mode. Pin detection and sampling options are selected by programming the ICON register.
Page 346: Figure 11-7. Interrupt Sampling
INTERRUPTS Figure 11-7 shows how a signal is sampled in each mode. The debounce-sampling option adds several clock cycles to an interrupt’s latency due to the multiple clocks of sampling. Inputs are sampled once every CLKIN cycle (external bus clock). Interrupt pins are asynchronous inputs.
Page 347: Table 11-1. Interrupt Control Registers Memory-Mapped Addresses
INTERRUPTS 11.7.3 Memory-Mapped Control Registers The programmer’s interface to the interrupt controller is through six memory-mapped control registers: ICON control register, IMAP0-IMAP2 control registers, IMSK register and IPND control register. Table 11-1 describes the ICU registers. Table 11-1. Interrupt Control Registers Memory-Mapped Addresses Register Name Description Address...
Page 348: Interrupt Control Register (Icon)
INTERRUPTS 11.7.4 Interrupt Control Register (ICON) The ICON register (see Figure 11-8) is a 32-bit memory-mapped control register that sets up the interrupt controller. Software can manipulate this register using the load/store type instructions. The ICON register is also automatically loaded at initialization from the control table in external memory.
Page 349: Interrupt Mapping Registers (Imap0-Imap2)
INTERRUPTS The global interrupts enable bit (bit 10) globally enables or disables the external interrupt pins and timer unit inputs. It does not affect the NMI pin. This bit performs the same function as clearing the mask register. The global interrupts enable bit is also changed indirectly by the use of the following instructions: inten intdis...
Page 350: Figure 11-9. Interrupt Mapping (Imap0-Imap2) Registers
INTERRUPTS External Interrupt 0 Field - IMAP0.x0 External Interrupt 1 Field - IMAP0.x1 External Interrupt 2 Field - IMAP0.x2 External Interrupt 3 Field - IMAP0.x3 Interrupt Map Register 0 (IMAP0) External Interrupt 4 Field - IMAP1.x4 External Interrupt 5 Field - IMAP1.x5 External Interrupt 6 Field - IMAP1.x6 External Interrupt 7 Field - IMAP1.x7 Interrupt Map Register 1 (IMAP1)
Page 351: Figure 11-10. Interrupt Pending (Ipnd) Register
INTERRUPTS 11.7.5.1 Interrupt Mask (IMSK) and Interrupt Pending (IPND) Registers The IMSK and IPND registers (see Figure 11-10 Figure 11-11) are both memory-mapped registers. Bits 0 through 7 of these registers are associated with the external interrupt pins (XINT0 through XINT7) and bits 12 and 13 are associated with the timer-interrupt inputs (TMR0 and TMR1).
Page 352: Figure 11-11. Interrupt Mask (Imsk) Registers
INTERRUPTS Dedicated External Interrupt Mask Bits - IMSK.xim (0) Masked (1) Not Masked Timer Interrupt Mask Bits - IMSK.tim (0) Masked (1) Not Masked Interrupt Mask Register (IMSK) Dedicated Mode Expanded External Interrupts Mask Bits - IMSK.eim (0) Masked (1) Not Masked Timer Interrupt Mask Bits - IMSK.tim (0) Masked (1) Not Masked...
Page 353: Interrupt Controller Register Access Requirements
INTERRUPTS The IPND register posts dedicated-mode interrupts originating from the eight external dedicated sources (when configured in dedicated mode) and the two timer sources. Asserting one of these inputs causes a 1 to be latched into its associated bit in the IPND register. In expanded mode, bits 0 through 7 of this register are not used and should not be modified;...
Page 354: Default And Reset Register Values
The interrupt controller, microcode and core resources handle all stages of interrupt service. Interrupt service is handled in the following stages: Requesting Interrupt — In the i960 Jx processor, the programmable on-chip interrupt controller transparently manages all interrupt requests. Interrupts are generated by hardware (external events) or software (the application program).
Page 355 INTERRUPTS Checking Pending Interrupts — The interrupt controller compares each pending interrupt’s priority with the current process priority. If process priority changes, posted interrupts of higher priority are then serviced. Comparing the process priority to posted interrupt priority is handled differently for hardware and software interrupts.
Page 356: Figure 11-12. Interrupt Controller
INTERRUPTS XINT0 XINT7 TINT0 TINT1 Interrupt Control Interrupt Detection Register Block Clear a Bit Pending Interrupts Global Interrupt Disable Interrupt Masks Interrupt Interrupt Pin Mode Selection Expanded-Mode Vector Interrupt Pin to Block Vector Map Registers 0 to 2 Vector Interrupt Core Interrupt Vector Action...
Page 357: Setting Up The Interrupt Controller
INTERRUPTS 11.8.1 Setting Up the Interrupt Controller This section provides an example of setting up the interrupt controller. The following example describes how the interrupt controller can be dynamically configured after initialization. Example 11-6 sets up the interrupt controller for expanded-mode operation. Initially the IMSK register is masked to allow for setup.
Page 358: Interrupt Context Switch
INTERRUPTS 11.8.3 Interrupt Context Switch When the processor services an interrupt, it automatically saves the interrupted program state or interrupt procedure and calls the interrupt handling procedure associated with the new interrupt request. When the interrupt handler completes, the processor automatically restores the interrupted program state.
Page 359: Servicing An Interrupt From Interrupted State
INTERRUPTS After completing the interrupt procedure, the processor: Copies the arithmetic controls field and the process controls field from the interrupt record into the AC and PC, respectively. It then switches to the executing state and restores the trace-enable bit to its value before the interrupt occurred. Deallocates the current stack frame and interrupt record from the interrupt stack and switches to the stack it was using before servicing the interrupt.
Page 360: Figure 11-13. Interrupt Service Flowchart
INTERRUPTS Expanded Interrupt Software Interrupt Dedicated Interrupt Non-Maskable Interrupt (NMI) get vector encoded get vector in field 1 vector = 248 set bit in IPND on XINT pins set corresponding IMSK pending bits in Stop ANDed with interrupt table IPND = 0? IMSK.eim = 1 Servicing...
Page 361: Interrupt Service Latency
11.9.2.1 Vector Caching Option To reduce interrupt latency, the i960 Jx processors allow some interrupt table vector entries to be cached in internal data RAM. When the vector cache option is enabled and an interrupt request has a cached vector to be serviced, the controller fetches the associated vector from internal RAM rather than from the interrupt table in memory.
Page 362: Caching Interrupt Routines And Reserving Register Frames
The time required to fetch the first instructions of an interrupt-handling procedure affects interrupt response time and throughput. The user can reduce this fetch time by caching interrupt procedures or portions of procedures in the i960 Jx processor’s instruction cache. The icctl instruction can load and lock these procedures into the instruction cache.
Page 363: Table 11-3. Base Interrupt Latency
INTERRUPTS 11.9.3 Base Interrupt Latency In many applications, the processor’s instruction mix and cache configuration are known suffi- ciently well to use typical interrupt latency in calculations of overall system performance. For example, a timer interrupt may frequently trigger a task switch in a multi-tasking kernel. Base interrupt latency assumes the following: •...
Page 364: Maximum Interrupt Latency
INTERRUPTS 11.9.4 Maximum Interrupt Latency In real-time applications, worst-case interrupt latency must be considered for critical handling of external events. For example, an interrupt from a mechanical subsystem may need service to calculate servo loop parameters to maintain directional control. Determining worst-case latency depends on knowledge of the processor’s instruction mix and operating environment as well as the interrupt controller configuration.
Page 365: Table 11-5. Worst-Case Interrupt Latency Controlled By Divo To Destination R3
INTERRUPTS Table 11-5. Worst-Case Interrupt Latency Controlled by divo to Destination r3 Worst Worst Worst Vector Detection 80960JA/JF 80960JD 80960JT (3x) Interrupt Type Caching Option Latency Latency Latency Enabled (Bus Clocks) (Bus Clocks) (Bus Clocks) Fast 30.5 Debounced 34.5 33.5 23.3 Fast 72+a...
Page 366: Table 11-7. Worst-Case Interrupt Latency When Delivering A Software Interrupt
INTERRUPTS Table 11-7. Worst-Case Interrupt Latency When Delivering a Software Interrupt Worst Worst Worst Vector Detection 80960JA/JF 80960JD 80960JT (1x) Interrupt Type Caching Option Latency Latency Latency Enabled (Bus Clocks) (Bus Clocks) (Bus Clocks) Fast 31.7+2c+d Debounced 35.7+2c+d 34+2c+d Fast 107+a 53+b 34.7+3c+d...
Page 367: Table 11-8. Worst-Case Interrupt Latency Controlled By Flushreg Of One Stack Frame
INTERRUPTS Table 11-8. Worst-Case Interrupt Latency Controlled by flushreg of One Stack Frame Worst Worst Worst Vector Detection 80960JA/JF 80960JD 80960JT (1x) Interrupt Type Caching Option Latency Latency Latency Enabled (Bus Clocks) (Bus Clocks) (Bus Clocks) Fast 77+a+b 41+d+e 28.3+A Debounced 81+a+b 43+d+e...
Page 368: Avoiding Certain Destinations For Mdu Operations
INTERRUPTS 11.9.4.1 Avoiding Certain Destinations for MDU Operations Typically, when delivering an interrupt, the processor attempts to push the first four local registers (pfp, sp, rip, and r3) onto the local register cache as early as possible. Because of register-interlock, this operation is stalled until previous instructions return their results to these registers.
Page 369 INITIALIZATION AND SYSTEM REQUIREMENTS...
Page 371: Overview
Reinitialization is useful for relocating data structures from ROM to RAM after initialization. The i960 Jx processor supports several facilities to assist in system testing and start-up diagnostics. ONCE mode electrically removes the processor from a system. This feature is useful for system-level testing where a remote tester exercises the processor system.
Page 372: Initialization
STEST pin. The processor then branches to the first instruction of user code. See Figure 12-1 for a flow chart of i960 Jx processor initialization. Hardware Reset Software Reinitialization Reset State...
Page 373: Reset State Operation
12-2. The reset state cannot be entered under direct control from user code. No reset instruction — or other condition that forces a reset — exists on the i960 Jx processors. The RESET pin must be asserted to enter the reset state. The processor does, however, provide a means to re-enter the initialization process.
Page 374: Figure 12-2. Cold Reset Waveform
INITIALIZATION AND SYSTEM REQUIREMENTS Figure 12-2. Cold Reset Waveform 12-4...
Page 375: Table 12-1. Reset States
INITIALIZATION AND SYSTEM REQUIREMENTS Table 12-1. Reset States Pins Reset State Pins Reset State AD31:0 Floating Low (read) DT/R Low (inactive) Low (receive) High (inactive) High (inactive) BLAST High (inactive) High (inactive) A3:2 LOCK/ ONCE Floating High (inactive) BE3:0 HOLDA High (inactive) Valid Output WIDTH/HLTD1:0...
Page 376: Self Test Function (Stest, Fail)
12.2.2 Self Test Function (STEST, FAIL) As part of initialization, the i960 Jx processor executes a bus confidence self test, an alignment check for data structures within the initial memory image (IMI), and optionally, an built-in self test program. The self test (STEST) pin enables or disables built-in self test. The FAIL pin indicates that the self tests passed or failed by asserting FAIL.
Page 377: The Stest Pin
INITIALIZATION AND SYSTEM REQUIREMENTS 12.2.2.1 The STEST Pin The STEST pin enables and disables Built-In Self Test (BIST). BIST can be disabled if the initial- ization time needs to be minimized or if diagnostics are simply not necessary. The STEST pin is sampled on the rising edge of the RESET input: •...
Page 378: Imi Alignment Check And System Error
INITIALIZATION AND SYSTEM REQUIREMENTS RESET Bus Confidence Test Status Internal Self-Test Status PASS PASS Bus Confidence Test Internal Self-Test FAIL FAIL FAIL Figure 12-3. FAIL Sequence 12.2.2.4 IMI Alignment Check and System Error The alignment check during initialization for data structures within the IMI ensures that the PRCB, control table, interrupt table, system-procedure table, and fault table are aligned to word boundaries.
Page 379: Architecturally Reserved Memory Space
Section 3.5, ”MEMORY ADDRESS SPACE” (pg. 3-13) shows the reserved address space. The i960 Jx suppresses all external bus cycles from 0 to 3FFH and from FF00 0000H to FFFF FFFFH. Addresses FEFF FF60H through FFFF FFFFH are reserved for implementation-specific functions.
Page 380: Initial Memory Image (Imi)
INITIALIZATION AND SYSTEM REQUIREMENTS The i960 Jx microprocessor uses the reserved address range 0000 0000H through 0000 03FFH for internal data RAM. This internal data RAM is used for storage of interrupt vectors plus general purpose storage available for application software variable allocation or data structures. Loads and stores directed to these addresses access internal memory;...
Page 381 INITIALIZATION AND SYSTEM REQUIREMENTS At initialization, the processor loads the Supervisor Stack Pointer (SSP) from the system procedure table, aligns it to a 16-byte boundary, and caches the pointer in the SSP memory-mapped control register (see section 3.3, “MEMORY-MAPPED CONTROL REGISTERS” (pg. 3-6)).
Page 382: Figure 12-4. Initial Memory Image (Imi) And Process Control Block (Prcb)
INITIALIZATION AND SYSTEM REQUIREMENTS Relocatable Data Structures Fixed Data Structures User Code: Init. Boot Record (IBR): Address Process Control Block (PRCB): PMCON FEFF FF30H Fault Table Base Address Byte 0 PMCON FEFF FF34H Control Table Base Address Byte 1 PMCON FEFF FF38H AC Register Initial Image Byte 2...
Page 383: Table 12-5. Initialization Boot Record
IBR can be accessed correctly. The lowest-order byte of each of the IBR’s first 4 words are used to form the register values. On the i960 Jx processor, the bytes at FEFF FF30 and FEFF FF34 are not needed, so the processor starts fetching at address FEFF FF38.
Page 384 INITIALIZATION AND SYSTEM REQUIREMENTS Example 12-1. Processor Initialization Flow Processor_Initialization_flow() FAIL_pin = true; restore_full_cache_mode; disable(I_cache); invalidate(I_cache); disable(D_cache); invalidate(D_cache); BCON.ctv = 0; /* Selects PMCON14_15 to control all accesses */ PMCON14_15 = 0; /* Selects 8-bit bus width */ /** Exit Reset State & Start_Init **/ if (STEST_ON_RISING_EDGE_OF_RESET) status = BIST();...
Page 385: Figure 12-5. Pmcon14_15 Register Bit Description In Ibr
INITIALIZATION AND SYSTEM REQUIREMENTS configuration table from the external control table. The Bus Configuration (BCON) register is also loaded at this time. The control table valid (BCON.ctv) bit is then set in the control table to validate the PMCON registers after they are loaded. In this way, the bus controller is completely configured during initialization.
Page 386: Process Control Block (Prcb)
INITIALIZATION AND SYSTEM REQUIREMENTS 12.3.1.2 Process Control Block (PRCB) The PRCB contains base addresses for system data structures and initial configuration information for the core and integrated peripherals. The base addresses are accessed from these internal registers. The registers are accessible to the users through the memory mapped interface. Upon reset or reinitialization, the registers are initialized.
Page 387: Figure 12-6. Process Control Block Configuration Words
INITIALIZATION AND SYSTEM REQUIREMENTS AC Register Initial Image Offset 08H Condition Code Bits - AC.cc Integer-Overflow Flag - AC.of (0) no overflow (1) overflow Integer Overflow Mask Bit - AC.om (0) enable overflow faults (1) mask overflow faults No-Imprecise-Faults Bit - AC.nif (0) allow imprecise fault conditions (1) prevent imprecise fault conditions Offset 0CH...
Page 388: Process Prcb Flow
INITIALIZATION AND SYSTEM REQUIREMENTS 12.3.2 Process PRCB Flow The following pseudo-code flow illustrates the processing of the PRCB. Note that this flow is used for both initialization and reinitialization (through sysctl Example 12-2. Process PRCB Flow Process_PRCB(prcb_ptr) PRCB_mmr = prcb_ptr; reset_state(data_ram);...
Page 389: Ac Initial Image
INITIALIZATION AND SYSTEM REQUIREMENTS 12.3.2.1 AC Initial Image The AC initial image is loaded into the on-chip AC register during initialization. The AC initial image allows the initial value of the overflow mask, no imprecise faults bit and condition code bits to be selected at initialization.
Page 390: Control Table
INITIALIZATION AND SYSTEM REQUIREMENTS The register cache and the configuration word are explained further in section 4.2, “LOCAL REGISTER CACHE” (pg. 4-2). 12.3.3 Control Table The control table is the data structure that contains the on-chip control registers values. It is automatically loaded during initialization and must be completely constructed in the IMI.
Page 391: Figure 12-7. Control Table
INITIALIZATION AND SYSTEM REQUIREMENTS Reserved (Initialize to 0) Reserved (Initialize to 0) Reserved (Initialize to 0) Reserved (Initialize to 0) Interrupt Map 0 (IMAP0) Interrupt Map 1 (IMAP1) Interrupt Map 2 (IMAP2) Interrupt Configuration (ICON) Physical Memory Region 0:1 Configuration (PMCON0_1) Reserved (Initialize to 0) Physical Memory Region 2:3 Configuration (PMCON2_3) Reserved (Initialize to 0)
Page 392: Device Identification On Reset
Model Manufacturer ID Figure 12-8. IEEE 1149.1 Device Identification Register The value for device identification is compliant with the IEEE 1149.1 specification and Intel standards. For specific DEVICEID, refer to the appropriate data sheet. Refer to section 1.4, “Related Documents” (pg.
Page 393: Startup Code Example
INITIALIZATION AND SYSTEM REQUIREMENTS After initialization, the software is responsible for copying data structures from ROM into RAM. The processor is then reinitialized with a new PRCB which contains the base addresses of the new data structures in RAM. Reinitialization is required to relocate any of the data structures listed below, since the processor caches the pointers to the structures.
Page 394 INITIALIZATION AND SYSTEM REQUIREMENTS Example 12-3. Initialization Header File (init.h) /*----------------------------------------------------------*/ init.h /*----------------------------------------------------------*/ #define BYTE_N(n,data) (((unsigned)(data) >> (n*8)) & 0xFF) typedef struct unsigned char bus_byte_0; unsigned char reserved_0[3]; unsigned char bus_byte_1; unsigned char reserved_1[3]; unsigned char bus_byte_2; unsigned char reserved_2[3]; unsigned char bus_byte_3;...
Page 395 INITIALIZATION AND SYSTEM REQUIREMENTS (Sheet 1 of 4) Example 12-4. Startup Routine (init.s) /*----------------------------------------------------------*/ init.s /*----------------------------------------------------------*/ /* initial PRCB .globl _rom_prcb .align 4 /* or .align 2 */ _rom_prcb: .word boot_flt_table 0 - Fault Table .word _boot_control_table # 4 - Control Table .word 0x00001000 8 - AC reg mask overflow fault...
Page 396 INITIALIZATION AND SYSTEM REQUIREMENTS (Sheet 2 of 4) Example 12-4. Startup Routine (init.s) .word (fault_proc<<2) + syscall # 3-Arithmetic Fault .word 0x27f .word # 4-Reserved .word .word (fault_proc<<2) + syscall # 5-Constraint Fault .word 0x27f .word # 6-Reserved .word .word (fault_proc<<2) + syscall # 7-Protection Fault .word...
Page 397 INITIALIZATION AND SYSTEM REQUIREMENTS (Sheet 3 of 4) Example 12-4. Startup Routine (init.s) .word _intx, _intx, _intx, _intx, _intx, _intx, _intx, _intx # e8 .word _intx, _intx, _intx, _intx, # f0 .word _nmi, 0, _intx, _intx, _intx, _intx # f8 /* START */ /* Processor starts execution here after reset.
Page 398 INITIALIZATION AND SYSTEM REQUIREMENTS (Sheet 4 of 4) Example 12-4. Startup Routine (init.s) /* Clear the IPND register */ 0xff008500, g0 0, g1 g1,(g0) callx _main #to main routine .globl _intr_stack .globl _user_stack .globl _supervisor_stack .bss _user_stack, 0x0200, 6 # default applica tion stack .bss _intr_stack, 0x0200, 6 # interrupt stack...
Page 399 INITIALIZATION AND SYSTEM REQUIREMENTS Example 12-6. Control Table (ctltbl.c) /*----------------------------------------------------------*/ ctltbl.c /*----------------------------------------------------------*/ #include "init.h" typedef struct unsigned control_reg[28]; }CONTROL_TABLE; const CONTROL_TABLE boot_control_table = { /* Reserved */ 0, 0, 0, 0, /* Interrupt Map Registers */ 0, 0, 0,/* Interrupt Map Regs (set by code as needed) */ 0x43bc, /* ICON - dedicated mode,...
Page 400 INITIALIZATION AND SYSTEM REQUIREMENTS (Sheet 1 of 2) Example 12-7. Initialization Boot Record File (rom_ibr.c) #include "init.h" * NOTE: The ibr must be located at 0xFEFFFF30. Use the linker to * locate this structure. The boot configuration is always region 14_15, since the IBR * must be located there extern void start_ip();...
Page 401 INITIALIZATION AND SYSTEM REQUIREMENTS (Sheet 2 of 2) Example 12-7. Initialization Boot Record File (rom_ibr.c) BYTE_N(3,BOOT_CONFIG), /* PMCON14_15 byte 4 */ 0,0,0, /* reserved set to 0 */ start_ip, &rom_prcb, CS_6 (Sheet 1 of 2) Example 12-8. Linker Directive File (init.ld) /*----------------------------------------------------------*/ init.ld /*----------------------------------------------------------*/...
Page 402 INITIALIZATION AND SYSTEM REQUIREMENTS (Sheet 2 of 2) Example 12-8. Linker Directive File (init.ld) SECTIONS .ibr : rom_ibr.o } > ibr .text : } > rom .data : } > data .bss : } > data rom_data = __Etext; /* used in init.s as source of .data section initial values.
Page 403 INITIALIZATION AND SYSTEM REQUIREMENTS Example 12-9. Makefile /*----------------------------------------------------------*/ makefile /*----------------------------------------------------------*/ LDFILE = init FINALOBJ = init OBJS = init.o ctltbl.o initmain.o IBR = rom_ibr.o LDFLAGS = -AJF -Fcoff -T$(LDFILE) -m ASFLAGS = -AJF -V CCFLAGS = -AJF -Fcoff -V -c init.ima: $(FINALOBJ) rom960 $(LDFILE) $(FINALOBJ) init: $(OBJS) $(IBR)
Page 404: System Requirements
V pins effectively reduces the impedance of power and ground connections to the chip and reduces transient noise induced by current surges. The i960 Jx processor is implemented in CHMOS IV technology. Unlike NMOS processes, power dissipation in the CHMOS process is due to capacitive charging and discharging on-chip and in the processor’s output buffers;...
Page 405: Power And Ground Planes
INITIALIZATION AND SYSTEM REQUIREMENTS 12.6.3 Pin Requirements In 3.3 V-only systems and systems that drive the i960 Jx processor pins from 3.3 V logic, connect the V pin directly to the 3.3 V V plane. In mixed voltage systems that drive the i960 Jx Processor inputs in excess of 3.3 V, the V must be connected to the system’s 5 V supply.
Page 406: Decoupling Capacitors
Also, for this reason, the capacitors should be low inductance. Chip capacitors (surface mount) exhibit lower inductance. 12.6.6 I/O Pin Characteristics The i960 Jx processor interfaces to its system through its pins. This section describes the general characteristics of the input and output pins. 12-36...
Page 407: Output Pins
INITIALIZATION AND SYSTEM REQUIREMENTS 12.6.6.1 Output Pins All output pins on the i960 Jx processor are three-state outputs. Each output can drive a logic 1 (low impedance to V ); a logic 0 (low impedance to V ); or float (present a high impedance to and V ).
Page 408: High Frequency Design Considerations
For the i960 Jx processor, two termination methods are attractive: AC and series. An AC termination matches the impedance of the trace, there by eliminating reflections due to the impedance mismatch.
Page 409: Latchup
Latchup is a condition in a CMOS circuit in which V becomes shorted to V . Intel’s CMOS IV processes are immune to latchup under normal operation conditions. Latchup can be triggered when the voltage limits on I/O pins are exceeded, causing internal PN junctions to become forward biased.
Page 410: Interference
INITIALIZATION AND SYSTEM REQUIREMENTS • Never apply power to an i960 Jx processor pin or a device connected to an i960 Jx processor pin before applying power to the i960 Jx processor itself. • Prevent overshoot and undershoot on I/O pins by adding line termination and by designing to reduce noise and reflection on signal lines.
Page 411: Figure 12-13. Avoid Closed-Loop Signal Paths
INITIALIZATION AND SYSTEM REQUIREMENTS F_CA082A Figure 12-13. Avoid Closed-Loop Signal Paths ESI is caused by the capacitive coupling of two adjacent conductors. The conductors act as the plates of a capacitor; a charge built up on one induces the opposite charge on the other. The following steps reduce ESI: •...
Page 413 MEMORY CONFIGURATION...
Page 415: Memory Attributes
13.1.1 Physical Memory Attributes The only programmable physical memory attribute for the i960 Jx microprocessor is the bus width, which can be 8-, 16- or 32-bits wide. For the purposes of assigning memory attributes, the physical address space is partitioned into 8, fixed 512 Mbyte regions determined by the upper three address bits.
Page 416: Logical Memory Attributes
13.1.2 Logical Memory Attributes The i960 Jx provides a mechanism for defining two logical memory templates (LMTs). An LMT may be used to specify the logical memory attributes for a section (or subset) of a physical memory subsystem connected to the BCU (e.g., DRAM, SRAM). The logical memory attributes defined by the i960 Jx are byte ordering and whether the information is cacheable or non-cacheable in the on-chip data cache.
Page 417: Differences With Previous I960 Processors
16 contiguous regions. When assigning physical memory attributes, the Jx divides memory into 8 contiguous, 512 Mbyte regions starting on 512 Mbyte boundaries. The logical memory templates of the i960 Jx processor provide a programmable association of logical memory addresses, whereas the i960 Cx processor assigns these attributes to the physical memory regions.
Page 418: Programming The Physical Memory Attributes (Pmcon Registers)
MEMORY CONFIGURATION 13.3 Programming the Physical Memory Attributes (PMCON Registers) The layout of the Physical Memory Configuration registers, PMCON0_1 through PMCON14_15, is shown in Figure 13-2, which gives the descriptions of the individual bits. The PMCON registers reside within memory-mapped control register space. Each PMCON register controls one 512-Mbyte region of memory according to the mapping shown in Table 13-1 Table 13-1.
Page 419: Bus Width
Bus Width The bus width for a region is controlled by the BW1:0 bits in the PMCON register. The operation of the i960 Jx processor with different bus width programming options is described in section 14.2.3.1, “Bus Width” (pg. 14-7).
Page 420: Bus Control (Bcon) Register
MEMORY CONFIGURATION 13.4.1 Bus Control (BCON) Register Immediately after a hardware reset, the PMCON register contents are marked invalid in the Bus Control (BCON) register. Figure 13-3 shows the BCON register and Control Table Valid (CTV) bit. Whenever the PMCON entries are marked invalid in BCON, the BCU uses the parameters in PMCON14_15 for all regions.
Page 421: Boundary Conditions For Physical Memory Regions
MEMORY CONFIGURATION 13.5 Boundary Conditions for Physical Memory Regions The following sections describe the operation of the PMCON registers during conditions other than “normal” accesses. 13.5.1 Internal Memory Locations The PMCON registers are ignored during accesses to internal memory or memory-mapped registers.
Page 422: Programming The Logical Memory Attributes
MEMORY CONFIGURATION 13.6 Programming the Logical Memory Attributes The bit/bit field definitions for the LMADR1:0 and LMMR1:0 registers are shown in Figure 13-4 Figure 13-5. LMCON registers reside within the memory-mapped control register space. Byte Order (read-only) 0 = Little endian 1 = Big endian Data Cache Enable 0 = Data caching disabled...
Page 423: Figure 13-5. Logical Memory Template Mask Registers (Lmmr0-1)
MEMORY CONFIGURATION Logical Memory Template Enabled 0 = LMT disabled 1 = LMT enabled Template Address Mask Reserved, write to zero Mnemonic Bit/Bit Field Name Bit Position(s) Function Defines upper 20 bits for the address mask for a logical memory template. The lower 12 Template Address bits are fixed at zero.
Page 424: Figure 13-6. Default Logical Memory Configuration Register (Dlmcon)
MEMORY CONFIGURATION The Default Logical Memory Configuration (DLMCON) register is shown in Figure 13-6. The BCU uses the parameters in the DLMCON register when the current access does not fall within one of the two logical memory templates (LMTs). Notice the byte ordering is controlled for the entire address space by programming the DLMCON register.
Page 425: Defining The Effective Range Of A Logical Data Template
MEMORY CONFIGURATION 13.6.1 Defining the Effective Range of a Logical Data Template For each logical data template, an LMADR register sets the base address using the A31:12 field. The LMMR register sets the address mask using the MA31:12 field. The effective address range for a logical data template is defined using the A31:12 field in an LMADRx register and the MA31:12 field in an LMMRx register.
Page 426: Selecting The Byte Order
The recommended, portable way to determine the byte-ordering associated with a logical memory template is to read the appropriate LMADR. The i960 Jx microprocessor supports this method by always ensuring that the DLMCON.be bit is reflected in bit zero of LMADR0 and LMADR1 (also labelled as LMADR.be) when they are read.
Page 427: Boundary Conditions For Logical Memory Templates
MEMORY CONFIGURATION 13.6.5 Initialization Immediately following a hardware reset, all LMTs are disabled. The LMTE bit in each of the LMMR registers is cleared (0) and all other bits are undefined. Immediately after a hardware reset the Default Logical Memory Control register (DLMCON) has the values shown in Table 13-2.
Page 428: Accesses Across Lmt Boundaries
MEMORY CONFIGURATION 13.6.6.3 Accesses Across LMT Boundaries Accesses that cross LMT boundaries should be avoided. These accesses are unaligned and broken into a number of smaller aligned accesses, which reside in one or the other LMT, but not both. Each smaller access is completed using the parameters of the LMT in which it resides. 13.6.7 Modifying the LMT Registers An LMT register can be modified using...
Page 429 EXTERNAL BUS...
Page 431: Bus Operation
14.1 OVERVIEW The bus is the data communication path between the various components of an i960 Jx micropro- cessor hardware system, allowing the processor to fetch instructions, manipulate data and interact with its I/O environment. To perform these tasks at high bandwidth, the processor features a burst transfer capability, allowing up to four successive 32-bit data transfers at a maximum rate of one word every clock cycle.
Page 432: Basic Bus States
EXTERNAL BUS The processor’s bus control unit is designed to decouple bus activity from instruction execution in the core as much as possible. When a load or store instruction or instruction prefetch is issued, a bus request is generated in the bus control unit. The bus control unit independently processes the request and retrieves data from memory for load instructions and instruction prefetches.
Page 433: Figure 14.1. Bus States With Arbitration
EXTERNAL BUS (READY AND BURST) OR NOT READY RECOVERED READY AND AND REQUEST NO BURST PENDING AND (NO HOLD OR LOCKED) REQUEST PENDING AND (NO HOLD OR RECOVERED LOCKED) RECOVERED AND REQUEST NO REQUEST AND PENDING NO REQUEST AND NO HOLD (NO HOLD OR AND (NO HOLD LOCKED)
Page 434: Bus Signal Types
14.2.2.1 Clock Signal The CLKIN input signal is the reference for all i960 Jx microprocessor signal timing relationships. Note that this is true even for the i960 JD processor, even though the CPU core runs at twice the CLKIN rate. Transitions on the AD31:2, AD1:0, A3:2, ADS, BE3:0, WIDTH/HLTD1:0, D/C, W/R, DEN, BLAST, RDYRCV, LOCK/ONCE, HOLD/HOLDA and BSTAT bus signal pins are always measured directly from the rising edge of CLKIN.
Page 435: Table 14-1. Summary Of I960 Jx Processor Bus Signals
EXTERNAL BUS Table 14-1. Summary of i960 Jx Processor Bus Signals Signal Name (Direction) Signal Function Symbol Word address, driven during Ta. Read or write AD31:2 Address/Data 31:2 (I/O) data, driven or sampled during Tw/Td. Address/Data 1:0 and Size 1:0 Number of transfers, driven during Ta.
Page 436: Bus Accesses
14.2.3 Bus Accesses The i960 Jx microprocessor uses the bus signals to transfer data between the processor and another component. The maximum transfer rate is achieved when performing burst accesses at the rate of four 32-bit data words per six clocks.
Page 437: Figure 14-2. Data Width And Byte Encodings
EXTERNAL BUS 14.2.3.1 Bus Width Each region’s data bus width is programmed in a Physical Memory Region Configuration (PMCON) register. The processor allows an 8-, 16- or 32-bit data bus width for each region. The processor places 8- and 16-bit data on low-order data pins, simplifying the interface to narrow bus external devices.
Page 438: Table 14-2. 8-Bit Bus Width Byte Enable Encodings
EXTERNAL BUS Table 14-2. 8-Bit Bus Width Byte Enable Encodings Byte (Not Used) (Not Used) (Used as A1) (Used as A0) Table 14-3. 16-Bit Bus Width Byte Enable Encodings Byte (Used as BHE) (Not Used) (Used as A1) (Used as BLE) Table 14-4.
Page 439: Basic Bus Accesses
32-bit read transaction. For simplicity, no wait states are shown. During the Ta state, the i960 Jx microprocessor transmits the address on the address/data lines. In the figure, the size bits (AD1:0) specify a single word transaction and WIDTH1:0 indicate a 32-bit wide access.
Page 440: Figure 14-3. Non-Burst Read And Write Transactions Without Wait States, 32-Bit Bus
EXTERNAL BUS Idle Write Read Idle CLKIN Invalid AD31:0 ADDR DATA Out ADDR A3:2 BE3:0 WIDTH1:0 BLAST DT/R RDYRCV F_JF030A Figure 14-3. Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus 14-10...
Page 441: Burst Transactions
14.2.3.3 Burst Transactions A burst access is an address cycle followed by two to four data transfers. The i960 Jx micropro- cessor uses burst transactions for instruction fetching and accessing system data structures. Therefore, a system design incorporating an i960 Jx microprocessor must support burst transac- tions.
Page 442: Figure 14-4. 32-Bit Wide Data Bus Bursts
EXTERNAL BUS A3:2 32-Bit Burst Bus Quad-Word Burst Triple-Word Burst Double-Word Burst Double-Word Burst Figure 14-4. 32-Bit Wide Data Bus Bursts A2:1 = (A2, BE1) 16-Bit Burst Bus 4 Short-Word Burst 2 Short-Word Burst 2 Short-Word Burst Figure 14-5. 16-Bit Wide Data Bus Bursts 14-12...
Page 443: Figure 14-6. 8-Bit Wide Data Bus Bursts
Notice that a new 16-byte boundary begins at address 10H. Since the processor stores 6 of the 12 bytes after this 16-byte boundary, the processor will split the transaction into a number of accesses. The i960 Jx processor cannot burst across 16-byte boundaries. 14-13...
Page 444: Figure 14-7. Unaligned Write Transaction
EXTERNAL BUS The processor splits the transaction into the following accesses. It performs the following bus cycles: Non-burst access to transfer the first short word (contents 5678H) to address 0AH. The short word at address 08H remains unchanged. Burst access to transfer the second and third short words (contents 1234H and 0FACEH) to address 0CH.
Page 445: Figure 14-8. Burst Read And Write Transactions W/O Wait States, 32-Bit Bus
EXTERNAL BUS CLKIN DATA DATA DATA DATA AD31:0 ADDR ADDR 00 or 01 01 or 11 A3:2 BE3:0 WIDTH1:0 BLAST DT/R RDYRCV Figure 14-8. Burst Read and Write Transactions w/o Wait States, 32-bit Bus 14-15...
Page 446: Figure 14-9. Burst Read And Write Transactions W/O Wait States, 8-Bit Bus
EXTERNAL BUS CLKIN DATA ADDR DATA DATA DATA AD31:0 ADDR 00,01,10 or 11 00,01,10 or 11 A3:2 BE1/A1 01 or 00 or 10 BE0/A0 WIDTH1:0 BLAST DT/R RDYRCV F_JF033A Figure 14-9. Burst Read and Write Transactions w/o Wait States, 8-bit Bus 14-16...
Page 447: Wait States
EXTERNAL BUS 14.2.3.4 Wait States Wait states lengthen the microprocessor’s bus cycles, allowing data transfers with slow memory and I/O devices. The 80960Jx supports three types of wait states: address-to-data, data-to-data and turnaround or recovery. All three types are controlled through the processor’s RDYRCV (Ready/Recover) pin, a synchronous input.
Page 448: Figure 14-10. Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus
EXTERNAL BUS CLKIN DATA DATA DATA DATA AD31:0 ADDR A3:2 BE3:0 WIDTH1:0 BLAST DT/R RDYRCV F_XL032A Figure 14-10. Burst Write Transactions With 2,1,1,1 Wait States, 32-bit Bus 14-18...
Page 449: Recovery States
14.2.3.5 Recovery States The state following the last data transfer of an access is a recovery (Tr) state. By default, i960 Jx microprocessor bus transactions have one recovery state. External logic can cause additional recovery states to be inserted by driving the RDYRCV pin low at the end of Tr.
Page 450: Figure 14-11. Burst Read/Write Transactions With 1,0 Wait States - Extra Tr State On Read, 16-Bit Bus
EXTERNAL BUS CLKIN DATA DATA ADDR AD31:0 ADDR 00,01,10, or 11 00,01,10, or 11 A3:2 BE1/A1 BE3/BHE BE0/BLE WIDTH1:0 BLAST DT/R RDYRCV F_XL034A Figure 14-11. Burst Read/Write Transactions with 1,0 Wait States - Extra Tr State on Read, 16-Bit Bus 14-20...
Page 451: Figure 14-12. Burst Read/Write Transactions With 1,0 Wait States, Extra Tr State
EXTERNAL BUS CLKIN DATA DATA ADDR ADDR AD31:0 00,01,10, or 11 00,01,10, or 11 A3:2 BE1/A1 BE3/BHE BE0/BLE WIDTH1:0 BLAST DT/R RDYRCV F_XL034A Figure 14-12. Burst Read/Write Transactions with 1,0 Wait States, Extra Tr State on Read, 16-Bit Bus 14-21...
Page 452: Bus And Control Signals During Recovery And Idle States
In cases where the core cancels a previously issued bus request, AD1:0 are indeterminate. 14.2.5 Data Alignment The i960 Jx microprocessor’s Bus Control Unit (BCU) directly supports both big-endian and little-endian aligned accesses. The processor also transparently supports both big-endian and little-endian unaligned accesses but with reduced performance. Unaligned accesses are broken down into a series of aligned accesses with the assistance of microcode executing on the processor.
Page 453: Table 14-5. Natural Boundaries For Load And Store Accesses
EXTERNAL BUS Table 14-5. Natural Boundaries for Load and Store Accesses Data Width Natural Boundary (Bytes) Byte Short Word Word Double Word Triple Word Quad Word Table 14-6. Summary of Byte Load and Store Accesses Address Offset from Accesses on 8-Bit Accesses on 16 Bit Accesses on 32 Bit Natural Boundary...
Page 454: Table 14-8. Summary Of N-Word Load And Store Accesses (N = 1, 2, 3, 4)
EXTERNAL BUS Table 14-8. Summary of n -Word Load and Store Accesses ( n = 1, 2, 3, 4) Address Offset Accesses on 32 Bit from Natural Accesses on 8-Bit Accesses on 16 Bit Bus Boundary in Bus (WIDTH1:0=00) (WIDTH1:0=01) (WIDTH1:0=10) Bytes +0 (aligned)
Page 455: Figure 14-13. Summary Of Aligned And Unaligned Accesses (32-Bit Bus)
EXTERNAL BUS Byte Offset Word Offset Short Access (Aligned) Byte, Byte Accesses Short-Word Load/Store Short Access (Aligned) Byte, Byte Accesses Word Access (Aligned) Byte, Short, Byte, Accesses Word Load/Store Short, Short Accesses Byte, Short, Byte Accesses One Double-Word Burst (Aligned) Byte, Short, Word, Byte Accesses Short, Word, Short Accesses Double-Word...
Page 456: Figure 14-14. Summary Of Aligned And Unaligned Accesses (32-Bit Bus) (Continued)
EXTERNAL BUS Byte Offset Word Offset One Three-Word Burst (Aligned) Byte, Short, Word, Word, Byte Accesses Short, Word, Word, Triple-Word Short Accesses Load/Store Byte, Word, Word, Short, Byte Accesses Word, Word, Word Accesses Word, Word, Word Accesses Word, Word, Word Accesses One Four-Word Burst (Aligned)
Page 457: Figure 14-15. Accesses Generated By Double Word Read Bus Request, Misaligned One Byte From Quad Word Boundary, 32-Bit Bus, Little Endian
EXTERNAL BUS CLKIN AD31:0 A3:2 BE3:0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 0 1 WIDTH1:0 Valid BLAST DT/R RDYRCV F_XL027A Figure 14-15. Accesses Generated by Double Word Read Bus Request, Misaligned One Byte From Quad Word Boundary, 32-Bit Bus, Little Endian 14-27...
Page 458: Byte Ordering And Bus Accesses
The default byte-order for both instruction and data accesses is programmed in the DLMCON register to be either little- or big-endian. On the i960 Jx processor, DLMCON.be controls the default byte order for internal (on-chip data ram and data cache) accesses as well as external accesses.
Page 459: Figure 14-16. Multi-Word Access To Big-Endian Memory Space
EXTERNAL BUS Table 14-10. Byte Ordering on Bus Transfers, Short-Word Data Type Short-Word Data Type Bus Pins (AD31:0) Addr Little Endian Big Endian Bits Xfer Width 31:24 23:16 15:8 31:24 23:16 15:8 A1, A0 32 bit 16 bit 8 bit Table 14-11.
Page 460: Atomic Bus Transactions
EXTERNAL BUS 14.2.7 Atomic Bus Transactions The atomic instructions, , consist of a load and store request to the same memory atadd and atmod location. Atomic instructions require indivisible, read-modify-write access to memory. That is, another bus agent must not access the target of the atomic instruction between read and write cycles.
Page 461: Bus Arbitration
14.2.8 Bus Arbitration The i960 Jx processor can share the bus with other bus masters, using its built-in arbitration protocol. The protocol assumes two bus masters: a default bus master (typically the 80960Jx) that controls the bus and another that requests bus control when it performs an operation (e.g., a DMA controller).
Page 462: Hold/Holda Protocol
HOLD may be asserted at any time so long as the transition meets the processors setup and hold requirements. HOLDA (hold acknowledge) is the processor’s output which indicates surrender of the bus. When the i960 Jx processor asserts HOLDA, it enters the Th (hold) state (see Figure 14.1).
Page 463: Bstat Signal
14.2.8.2 BSTAT Signal The i960 Jx microprocessor extends the HOLD/HOLDA protocol with a bus status (BSTAT) signal. In simplest terms, assertion of the BSTAT output pin indicates that the CPU may soon stall unless it obtains (or retains) control of the bus. This indication is a useful input to arbitration logic, whether or not the 80960 Jx is the primary bus master.
Page 464: Bus Applications
EXTERNAL BUS • A load request has been issued to the BCU. This behavior promotes performance by supporting early data loading. • A special operation is underway that requires emptying the bus queue. Examples of such operations are execution of the HALT instruction and register stores that control logical or physical memory configuration.
Page 465: Figure 14-19. Generalized 80960Jx System With 80960 Local Bus
I/O devices to the local bus, as in Figure 14-19. These systems are more complex, but performance and flexibility improve because bus traffic is partitioned away from the i960 Jx processor’s local bus. An example of such a system might be a network hub. i960 Jx...
Page 466: Figure 14-21. 80960Jx System With 80960 Local Bus, Pci Local Bus And Local Bus For High End Microprocessor
14-21. In this way, the i960Jx can improve the performance of complex systems such as servers by sparing the main system CPU and its local memory the task of buffering low-level I/O. Base i960 Jx Local Memory Processor 80960 Local Bus...
Page 467: Memory Subsystems
14.3.1.1 Memory Subsystems Memory systems for the i960 Jx processor include a mix of non-volatile and volatile devices including ROM, DRAM, SRAM or flash memory. The circuit designer may take advantage of programmable bus width to optimize the number of devices in each memory array. For example, the processor can boot from a single, slow, 8-bit ROM device, then execute from code loaded to a faster, wider and larger RAM array.
Page 469 TEST FEATURES...
Page 471: On-Circuit Emulation (Once)
The i960 Jx processor uses the dual function LOCK/ONCE pin for ONCE. The LOCK/ONCE pin is an input while RESET is asserted. The i960 Jx processor uses this pin as an output when the ONCE mode conditions are not present.
Page 472: Boundary Scan (Jtag)
15.2 BOUNDARY SCAN (JTAG) The i960 Jx processor provides test features compatible with IEEE Standard Test Access Port and Boundary Scan Architecture (IEEE Std. 1149.1). JTAG ensures that components function correctly, connections between components are correct, and components interact correctly on the printed circuit board.
Page 473: Tap Elements
TEST FEATURES 15.2.1.4 TAP Elements The Test Access Port (TAP) contains a TAP controller, an instruction register, a group of test data registers, and the TAP pins as shown in the block diagram in Figure 15-1. The TAP is the general-purpose port that provides access to the test data registers and instruction registers through the TAP controller.
Page 474: Figure 15-2. Tap Controller State Diagram
TEST FEATURES TRST TEST - LOGIC - RESET RUN - TEST / SELECT- SELECT- DR - SCAN IDLE IR - SCAN CAPTURE - IR CAPTURE - DR SHIFT - DR SHIFT - IR EXIT1 - IR EXIT1 - DR PAUSE - DR PAUSE - IR EXIT2 - DR EXIT2 - IR...
Page 475: Tap Registers
TEST FEATURES The i960 Jx processor’s TAP is composed of four input connections (TMS, TCK, TRST and TDI) and one output connection (TDO). These pins are described in Table 15-1. Table 15-1. TAP Controller Pin Definitions Pin Name Mnemonic Type...
Page 476: Tap Test Data Registers
15.3.2 TAP Test Data Registers The i960 Jx processor contains a device identification register and three test data registers (Bypass, Boundary-Scan and RUNBIST). Each test data register selected by the TAP controller is connected serially between TDI and TDO. TDI is connected to the test data register’s most significant bit.
Page 477: Runbist Register
The Boundary-Scan register is a required set of serial-shiftable register cells, configured in master/slave stages and connected between each of the i960 Jx processor’s pins and on-chip system logic. Pins NOT in the Boundary-Scan chain are power, ground and JTAG pins.
Page 478: Ieee Required Instructions
TEST FEATURES 15.3.3 Boundary Scan Instruction Set The i960 Jx processor supports three mandatory boundary scan instructions bypass . The i960 Jx processor also contains two additional public instructions sample preload extest idcode runbist Table 15-2 lists the i960 Jx processor’s boundary scan instruction codes.
Page 479: Tap Controller
After loading runbist instruction code into the instruction register, the TAP runbist bist controller must be placed in the Run-Test/Idle state. begins on the first i960 Jx rising edge of TCK after the Run-Test/Idle state is entered. The TAP controller 0111 2 bist must remain in the Run-Test/Idle state until is completed.
Page 480: Test Logic Reset State
15.3.5.1 Test Logic Reset State In this state, test logic is disabled to allow normal operation of the i960 Jx processor. Test logic is disabled by loading the IDCODE register. No matter what the state of the controller, it enters Test-Logic-Reset state when the TMS input is held high (1) for at least five rising edges of TCK.
Page 481: Shift-Dr State
TEST FEATURES If TMS is high on the rising edge of TCK, the controller enters the Exit1-DR. If TMS is low on the rising edge of TCK, the controller enters the Shift-DR state. 15.3.5.5 Shift-DR State In this controller state, the test data register, which is connected between TDI and TDO as a result of the current instruction, shifts data one bit position nearer to its serial output on each rising edge of TCK.
Page 482: Update-Dr State
TEST FEATURES 15.3.5.9 Update-DR State The Boundary-Scan register is provided with a latched parallel output. This output prevents changes at the parallel output while data is shifted in response to the extest sample preload instructions. When the Boundary-Scan register is selected while the TAP controller is in the Update-DR state, data is latched onto the Boundary-Scan register’s parallel output from the shift-register path on the falling edge of TCK.
Page 483: Exit1-Ir State
TEST FEATURES If TMS is held high on the rising edge of TCK, the controller enters the Exit1-IR state. If TMS is held low on the rising edge of TCK, the controller remains in the Shift-IR state. 15.3.5.13 Exit1-IR State This is a temporary state.
Page 484: Boundary-Scan Register
HIGHZ pins. Table 15-2 shows the bit order of the i960 Jx processor Boundary-Scan register. All table cells that contain “CTL” select the direction of bidirectional pins or HIGHZ output pins. If a “1” is loaded into the control cell, the associated pin(s) are HIGHZ or selected as input.
Page 485: Example
TEST FEATURES 15.3.6.1 Example In the example that follows, two command actions are described. The example starts in the reset state, a new instruction is loaded and executed. See Figure 15-3 for a JTAG example. The steps are: Load the instruction into the Instruction Register: sample preload...
Page 486: Figure 15-3. Jtag Example
TEST FEATURES 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 Don’t Care IR Shift Reg Don’t Care 4 bits long Parallel Out...
Page 487: Figure 15-4. Timing Diagram Illustrating The Loading Of Instruction Register
TEST FEATURES Controller State Data input to IR IR shift-register IDCODE NEW INSTRUCTION Parallel output of IR Data input to TDR TDR shift-register Parallel output of TDR OLD DATA INSTRUCTION REGISTER Register selected INACTIVE INACTIVE ACTIVE INACTIVE TDO enable = Don’t care or undefined Figure 15-4.
Page 488: Boundary Scan Description Language Example
TEST FEATURES Controller State Data input to IR IR shift-register INSTRUCTION ID CODE Parallel output of IR Data input to TDR TDR shift-register OLD DATA NEW DATA Parallel output of TDR TEST DATA REGISTER Register Selected INACTIVE ACT. INACTIVE ACTIVE INACTIVE TDO enable = Don’t care or undefined...
Page 489 (Sheet 1 of 4) Example 15-1. Boundary Scan Description Language Example -- i960® Jx Processor BSDL Model -- The following list describes all of the pins that are contained in the i960 Jx -- microprocessor. entity JX_Processor is generic(PHYSICAL_PIN_MAP : string := "PGA_14x14");...
Page 490 TEST FEATURES (Sheet 2 of 4) Example 15-1. Boundary Scan Description Language Example AVCC : linkage bit; : linkage bit_vector(1 to 3)); use STD_1149_1_1990.all; use i960JX_a.all; --This list describes the physical pin layout of all signals attribute PIN_MAP of JX_Processor : entity is PHYSICAL_PIN_MAP; constant PGA_14x14 : PIN_MAP_STRING := -- Define PinOut of PGA "TDI...
Page 491 TEST FEATURES (Sheet 3 of 4) Example 15-1. Boundary Scan Description Language Example "RUNBIST (0111)," & "Reserved (1100, 1011)"; attribute Instruction_Capture of JX_Processor: entity is "0001"; -- there is no Instruction_Disable attribute for JX_Processor attribute Instruction_Private of JX_Processor: entity is "Reserved" ; --attribute Instruction_Usage of JX_Processor: entity is "RUNBIST (registers Runbist;...
Page 492 TEST FEATURES (Sheet 4 of 4) Example 15-1. Boundary Scan Description Language Example "21 (CBSC_1, AD(17), bidir, X, 15, 1, Z)," & "22 (CBSC_1, AD(18), bidir, X, 15, 1, Z)," & "23 (CBSC_1, AD(19), bidir, X, 15, 1, Z)," & "24 (CBSC_1, AD(20), bidir, X, 15, 1, Z),"...
Page 493 CONSIDERATIONS FOR WRITING PORTABLE CODE...
Page 495: A.1 Core Architecture
APPENDIX A CONSIDERATIONS FOR WRITING PORTABLE CODE This appendix describes the aspects of the microprocessor that are implementation-dependent. The following information is intended as a guide for writing application code that is directly portable to ® other i960 architecture implementations. CORE ARCHITECTURE All i960 microprocessor family products are based on the core architecture definition.
Page 496: A.2 Address Space Restrictions
Addresses in the range FF00 0000H to FFFF FFFFH are reserved by the i960 architecture. The i960 Jx processor cannot access this memory, so any use of reserved memory by other i960 processor code is not portable to the i960 Jx processor.
Page 497: A.3 Data And Data Structure Alignment
(for I/O or shared data in a multiprocessor system) and cacheable regions (local system memory) with no external hardware logic. To maintain data cache coherency, the i960 Jx processor implements a simple single processor coherency mechanism. Also, by software control, the data cache can be globally enabled, globally disabled or globally invalidated.
Page 498: A.4 Reserved Locations In Registers And Data Structures
The N parameter is defined by the following expression: SALIGN*16 = 2 . Thus for the i960 Jx processors, N is 4. RESERVED LOCATIONS IN REGISTERS AND DATA STRUCTURES Some register and data structure fields are defined as reserved locations. A reserved field may be used by future implementations of the i960 architecture.
Page 499: A.5.2 Implementation-Specific Instructions
Code that accesses locations in initialization data structures is not portable to other i960 processor implementations. The i960 Jx processors use an initialization boot record (IBR) and a process control block (PRCB) to hold initial configuration and a first instruction pointer.
Page 500: A.8 Memory Configuration
The i960 Jx processors do not store a resumption record for suspended instructions in the interrupt or fault record. Portable programs must tolerate interrupt stack frames with and without these resumption records.
Page 501: A.10.1 Data Control Peripheral Units
A.10.2 Timers The i960 Jx processor contains two 32-bit timers that are implementation-specific extensions to the i960 architecture. Code involving operation, setup and control of the timers may or may not be directly portable to other i960 processors.
Page 503 OPCODES AND EXECUTION TIMES...
Page 505: B.1 Instruction Reference By Opcode
APPENDIX B OPCODES AND EXECUTION TIMES INSTRUCTION REFERENCE BY OPCODE This section lists the instruction encoding for each i960® Jx processor instruction. Instructions are grouped by instruction format and listed by opcode within each format. Table B-1. Miscellaneous Instruction Encoding Bits Description REG Format —...
Page 506: Table B-2. Reg Format Instruction Encodings
OPCODES AND EXECUTION TIMES (Sheet 1 of 4) Table B-2. REG Format Instruction Encodings 31..24 23 ..19 18 . 14 10 ... 7 4 ... 0 58:0 notbit 0101 1000 0000 bitpos 58:1 0101 1000 src2 0001 src1 andnot src2 src1 58:2...
Page 507 OPCODES AND EXECUTION TIMES (Sheet 2 of 4) Table B-2. REG Format Instruction Encodings 31 ..24 23.. 19 18 . .14 10 ...7 4 ..0 5A:2 concmpo 0101 1010 src2 0010 src1 5A:3 concmpi 0101 1010 src2 0011 src1 cmpinco src2...
Page 508 OPCODES AND EXECUTION TIMES (Sheet 3 of 4) Table B-2. REG Format Instruction Encodings 31..24 23 ..19 18 . 14 10 ... 7 4 ... 0 65:D 0110 0101 1101 src1 halt 66:0 calls 0110 0110 0000 66:B mark 0110 0110 1011 66:C...
Page 509 OPCODES AND EXECUTION TIMES (Sheet 4 of 4) Table B-2. REG Format Instruction Encodings 31 ..24 23.. 19 18 . .14 10 ...7 4 ..0 7B:1 addige 0111 1011 src2 0001 src1 7B:2 suboge 0111 1011 src2 0010 src1 subige src2...
Page 510: Table B-3. Cobr Format Instruction Encodings
OPCODES AND EXECUTION TIMES Table B-3. COBR Format Instruction Encodings 31 ... 24 23 . 19 18... 14 12 ..2 testno 0010 0000 testg 0010 0001 teste 0010 0010 testge 0010 0011 testl 0010 0100 testne 0010 0101 testle 0010 0110 testo 0010 0111...
Page 511: Table B-4. Ctrl Format Instruction Encodings
OPCODES AND EXECUTION TIMES Table B-4. CTRL Format Instruction Encodings 31....24 23...2 1 + 1 0000 1000 targ call 0000 1001 targ 0000 1010 1 + 1 0000 1011 targ 1 + 1 0001 0000 targ 1 + 1 0001 0001 targ 1 + 1 0001 0010...
Page 512: Table B-6. Cycle Counts For Icctl Operations
OPCODES AND EXECUTION TIMES Table B-6. Cycle Counts for icctl Operations Operation Cycles to Execute Disable I-cache Enable I-cache Invalidate I-cache Load and Lock I-cache 5193 I-cache Status Request I-cache Locking Status Table B-7. Cycle Counts for dcctl Operations Operation Cycles to Execute Disable D-cache Enable D-cache...
Page 513: Table B-9. Mem Format Instruction Encodings
OPCODES AND EXECUTION TIMES Table B-9. MEM Format Instruction Encodings 31 ..24 23 ...19 18 ..14 13 ..12 11..........0 Opcode src/dst ABASE Mode Offset 31 ..24 23 ...19 18 ..14 13 ..12 .. 11 ..10 9..7 6 .. 5 4 ..0 Opcode src/dst ABASE...
Page 514: Table B-10. Addressing Mode Performance
OPCODES AND EXECUTION TIMES Table B-10. Addressing Mode Performance Number of Memory Cycles to Mode Assembler Syntax Instruction Format Execute words Absolute Offset MEMA Absolute Displacement MEMB Register Indirect (reg) MEMB Register Indirect with Offset exp(reg) MEMA Register Indirect with Displacement exp(reg) MEMB Index with Displacement exp[reg*scale]...
Page 515 MACHINE-LEVEL INSTRUCTION FORMATS...
Page 517: C.1 General Instruction Format
APPENDIX C MACHINE-LEVEL INSTRUCTION FORMATS ® This appendix describes the encoding format for instructions used by the i960 processors. Included is a description of the four instruction formats and how the addressing modes relate to these formats. Refer also to APPENDIX B, OPCODES AND EXECUTION TIMES.
Page 518: C.2 Reg Format
MACHINE-LEVEL INSTRUCTION FORMATS Table C-1. Instruction Field Descriptions Instruction Field Description The opcode of the instruction. Opcode encodings are defined in section 6.1.8, Opcode “Opcode and Instruction Format” (pg. 6-6). An input to the instruction. This field specifies a value or address. In one case of the src1 COBR format, this field is used to specify a register in which a result is stored.
Page 519: Figure 5-1. Machine-Level Instruction Formats
MACHINE-LEVEL INSTRUCTION FORMATS Table C-2. Encoding of src1 and src2 in REG Format Src1 or Src2 Operand M1 or M2 Register Number Literal Value Value 00000 ... 01111 r0 ... r15 10000 ... 11111 g0 ... g15 00000 ... 11111 0 ...
Page 520: C.4 Ctrl Format
MACHINE-LEVEL INSTRUCTION FORMATS Table C-5. Encoding of src2 in COBR Format src2 g0 ... g15 r0 ... r15 reserved The displacement field contains a signed two’s complement number that specifies a word displacement. The processor uses this value to compute the address of a target instruction to which the processor branches as a result of the comparison.
Page 521: C.5.1 Mema Format Addressing
MACHINE-LEVEL INSTRUCTION FORMATS The mode field determines the address mode used for the instruction. Table C-6 summarizes the addressing modes for the two MEM-format encodings. Fields used in these addressing modes are described in the following sections. Table C-6. Addressing Modes for MEM Format Instructions # of Instr Format MODE...
Page 522: C.5.2 Memb Format Addressing
MACHINE-LEVEL INSTRUCTION FORMATS For the register-indirect-with-offset addressing mode (MODE = 10), offset field value is added to the address in the abase register. Clearing the offset value creates a register indirect addressing mode; however, this operation can generally be carried out faster by using the MEMB version of this addressing mode.
Page 523 REGISTER AND DATA STRUCTURES...
Page 525 APPENDIX D REGISTER AND DATA STRUCTURES This appendix is a compilation of all register and data structure figures described throughout the manual. Following each figure is a reference that indicates 23the section that discusses the figure. Table D-1. Register and Data Structures (Sheet 1 of 2) Fig.
Page 526 REGISTER AND DATA STRUCTURES Table D-1. Register and Data Structures (Sheet 2 of 2) Fig. Register / Data Structure Where Defined in the manual Page Section 12.3.1.2, “Process Control Block (PRCB)” D-22 Process Control Block Configuration Words D-21 (pg. 12-16) Section 12.3.3, “Control Table”...
Page 527: Figure D-1. Ac (Arithmetic Controls) Register
REGISTER AND DATA STRUCTURES REGISTERS No-Imprecise-Faults Bit- AC.nif (0) Some Faults are Imprecise (1) All Faults are Precise Integer Overflow Mask Bit - AC.om (0) No Mask (1) Mask Integer-Overflow Flag - AC.of (0) No Overflow (1) Overflow Condition Code Bits - AC.cc Reserved (Initialize to 0) Figure D-1.
Page 528: Figure D-2. Pc (Process Controls) Register
REGISTER AND DATA STRUCTURES Trace-Enable Bit - PC.te (0) Globally disable trace faults (1) Globally enable trace faults Execution-Mode Flag - PC.em (0) user mode (1) supervisor mode Trace-Fault-Pending - PC.tfp (0) no fault pending (1) fault pending State Flag - PC.s (0) executing (1) interrupted Priority Field - PC.p...
Page 529: Figure D-3. Procedure Stack Structure And Local Registers
REGISTER AND DATA STRUCTURES Procedure Stack Previous Frame Pointer (PFP) Current Register Set Stack Pointer (SP) Previous Stack Return Instruction Pointer (RIP) Frame Frame Pointer (FP) user allocated stack padding area Previous Frame Pointer (PFP) Stack Pointer (SP) register Current reserved for RIP save area Stack...
Page 530: Figure D-4. System Procedure Table
REGISTER AND DATA STRUCTURES 000H 008H supervisor stack pointer base 00CH 010H Trace Control 02CH 030H procedure entry 0 034H procedure entry 1 procedure entry 2 038H 03CH 438H 43CH procedure entry 259 Procedure Entry address Reserved Entry Type: (Initialize to 0) 00 - Local 10-Supervisor Preserved...
Page 531: Figure D-5. Pfp (Previous Frame Pointer) Register (R0
REGISTER AND DATA STRUCTURES Return Status Return-Type Field - PFP.rt Pre-Return-Trace Flag - PFP.p Previous Frame Pointer Address-PFP.a Figure D-5. PFP (Previous Frame Pointer) Register (r0) Section 7.8, “RETURNS” (pg. 7-20)
Page 532: Figure D-6. Fault Table And Fault Table Entries
REGISTER AND DATA STRUCTURES Fault Table PARALLEL/OVERRIDE Fault Entry TRACE Fault Entry OPERATION Fault Entry ARITHMETIC Fault Entry CONSTRAINT Fault Entry PROTECTION Fault Entry TYPE Fault Entry Local-Call Entry Fault-Handler Procedure Address System-Call Entry Fault-Handler Procedure Number 0000 027FH Reserved (Initialize to 0) Figure D-6.
Page 533: Figure D-7. Fault Record
REGISTER AND DATA STRUCTURES NFP - (n+1)*32 FAULT DATA NFP - 24- n*32 NFP - 20- n*32 NFP - 12- n*32 FSUBTYPE (n) FTYPE (n) NFP - 8- n*32 ADDRESS OF FAULTING INSTRUCTION (n) NFP - 4- n*32 NFP - 64 RESUMPTION INFORMATION NFP - 52 NFP - 48...
Page 534: Figure D-8. Tc (Trace Controls) Register
REGISTER AND DATA STRUCTURES Trace Mode Bits Instruction Trace Mode - TC.i Branch Trace Mode - TC.b Call Trace Mode -TC.c Return Trace Mode - TC.r Pre-Return Trace Mode - TC.p Supervisor Trace Mode - TC.s Mark Trace Mode - TC.mk Hardware Breakpoint Event Flags Instruction-Address Breakpoint 0 - TC.i0f Instruction-Address Breakpoint 1 - TC.i1f...
Page 535: Figure D-10. Dab (Data Address Breakpoint) Register Format
REGISTER AND DATA STRUCTURES Data Address Hardware Reset Value: 0000 0000H Software Re-init Value: 0000 0000H Figure D-10. DAB (Data Address Breakpoint) Register Format Section 9.2.7.5, “Data Address Breakpoint (DAB) Registers” (pg. 9-9) IPBx Mode Instruction Address Hardware Reset Value: 0000 0000H Software Re-init Value: 0000 0000H Figure D-11.
Page 536: Figure D-12. Tmr0-1 (Timer Mode Register
REGISTER AND DATA STRUCTURES Terminal Count Status - TMRx.tc (0) No Terminal Count (1) Terminal Count Timer Enable - TMRx.enable (0) Disabled (1) Enabled Timer Auto Reload Enable - TMRx.reload (0) Auto Reload Disabled (1) Auto Reload Enabled Timer Register Supervisor Write Control - TMRx.sup (0) Supervisor and User Mode Write Enabled (1) Supervisor Mode Only Write Enabled Timer Input Clock Selects - TMRx.csel1:0...
Page 537: Figure D-14. Trr0-1 (Timer Reload Register
REGISTER AND DATA STRUCTURES Timer Auto-Reload Value - TRRx.d31:0 D31:0 Timer Reload Register (TRR0, TRR1) Figure D-14. TRR0-1 (Timer Reload Register) Section 10.1.3, “Timer Reload Register (TRR0, TRR1)” (pg. 10-7) D-13...
Page 538: Figure D-15. Interrupt Table
REGISTER AND DATA STRUCTURES 000H Pending Priorities 004H Pending Interrupts 020H 024H (Vector 8) Entry 8 028H (Vector 9) Entry 9 02CH (Vector 10) Entry 10 Entry 243 3D0H (Vector 243) 3D4H (Vector 244) 3E0H (Vector 247) 3E4H (Vector 248) NMI Vector 3E8H (Vector 249) 3F0H (Vector 251)
Page 539: Figure D-16. Storage Of An Interrupt Record On The Interrupt Stack
REGISTER AND DATA STRUCTURES Current Stack (Local, Supervisor, or Interrupt Stack) Current Frame Interrupt Stack Padding Area Optional Data Stack (not used by 80960Jx) Growth Saved Process Controls Register NFP-16 Interrupt Saved Arithmetic Controls Register NFP-12 Record Vector Number NFP-8 New Frame Reserved Figure D-16.
Page 540: Figure D-17. Icon (Interrupt Control) Register
REGISTER AND DATA STRUCTURES Interrupt Mode - ICON.im (00) Dedicated (01) Expanded (10) Mixed (11) Reserved Signal Detection Mode - ICON.sdm (0) Level-low activated (1) Falling-edge activated Global Interrupts Enable - ICON.gie (0) Enabled (1) Disabled Mask Operation - ICON.mo (00) Move to r3, mask unchanged (01) Move to r3 and clear for dedicated mode interrupts (10) Move to r3 and clear for expanded mode interrupts...
Page 541: Figure D-18. Imap0-Imap2 (Interrupt Mapping) Registers
REGISTER AND DATA STRUCTURES External Interrupt 0 Field - IMAP0.x0 External Interrupt 1 Field - IMAP0.x1 External Interrupt 2 Field - IMAP0.x2 External Interrupt 3 Field - IMAP0.x3 Interrupt Map Register 0 (IMAP0) External Interrupt 4 Field - IMAP1.x4 External Interrupt 5 Field - IMAP1.x5 External Interrupt 6 Field - IMAP1.x6 External Interrupt 7 Field - IMAP1.x7 Interrupt Map Register 1 (IMAP1)
Page 542: Figure D-19. Imsk (Interrupt Mask) Registers
REGISTER AND DATA STRUCTURES Dedicated External Interrupt Mask Bits - IMSK.xim (0) Masked (1) Not Masked Timer Interrupt Mask Bits - IMSK.tim (0) Masked (1) Not Masked Interrupt Mask Register (IMSK) Dedicated Mode Expanded External Interrupts Mask Bits - IMSK.eim (0) Masked (1) Not Masked Timer Interrupt Mask Bits - IMSK.tim...
Page 543: Figure D-20. Interrupt Pending (Ipnd) Register
REGISTER AND DATA STRUCTURES External Interrupt Pending Bits - IPND.xip (0) No Interrupt (1) Pending Interrupt Timer Interrupt Pending Bits - IPND.tip (0) No Interrupt (1) Pending Interrupt Interrupt Pending Register (Dedicated Mode) Timer Interrupt Pending Bits - IPND.tip (0) No Interrupt (1) Pending Interrupt Interrupt Pending Register (Expanded Mode) External Interrupt Pending Bits - IPND.xip...
Page 544: Figure D-21. Initial Memory Image (Imi) And Process Control Block (Prcb
REGISTER AND DATA STRUCTURES Relocatable Data Structures Fixed Data Structures User Code: Init. Boot Record (IBR): Address Process Control Block (PRCB): PMCON FEFF FF30H Fault Table Base Address Byte 0 PMCON FEFF FF34H Control Table Base Address Byte 1 PMCON FEFF FF38H AC Register Initial Image Byte 2...
Page 545: Figure D-22. Process Control Block Configuration Words
REGISTER AND DATA STRUCTURES AC Register Initial Image Offset 08H Condition Code Bits - AC.cc Integer-Overflow Flag - AC.of (0) no overflow (1) overflow Integer Overflow Mask Bit - AC.om (0) enable overflow faults (1) mask overflow faults No-Imprecise-Faults Bit - AC.nif (0) allow imprecise fault conditions (1) prevent imprecise fault conditions Offset 0CH...
Page 546: Figure D-23. Control Table
REGISTER AND DATA STRUCTURES Reserved (Initialize to 0) Reserved (Initialize to 0) Reserved (Initialize to 0) Reserved (Initialize to 0) Interrupt Map 0 (IMAP0) Interrupt Map 1 (IMAP1) Interrupt Map 2 (IMAP2) Interrupt Configuration (ICON) Physical Memory Region 0:1 Configuration (PMCON0_1) Reserved (Initialize to 0) Physical Memory Region 2:3 Configuration (PMCON2_3) Reserved (Initialize to 0)
Page 547: Figure D-24. Ieee 1149.1 Device Identification Register
REGISTER AND DATA STRUCTURES Part Number Product Type Version Model Manufacturer ID Figure D-24. IEEE 1149.1 Device Identification Register Section 12.4, “DEVICE IDENTIFICATION ON RESET” (pg. 12-22) Bus Width 00 = 8-bit 01 = 16-bit Reserved, 10 = 32-bit bus write to zero 11 = reserved (do not use) Figure D-25.
Page 548: Figure D-26. Bcon (Bus Control) Register
REGISTER AND DATA STRUCTURES Configuration Entries in Control Table Valid (BCON.ctv) 0 = PMCON entries not valid; use PMCON15 setting. 1 = PMCON entries valid Internal RAM Protection (BCON.irp) 0 = Internal data RAM not protected from user mode writes 1 = Internal data RAM protected from user mode writes Supervisor Internal RAM Protection (BCON.sirp) 0 = First 64 bytes not protected from supervisor mode writes...
Page 549: Figure D-28. Lmadr0:1 Logical Memory Template Starting Address Registers
REGISTER AND DATA STRUCTURES Byte Order (read-only) 0 = Little endian 1 = Big endian Data Cache Enable 0 = Data caching disabled 1 = Data caching enabled Template Starting Address Reserved, write to zero Figure D-28. LMADR0:1 Logical Memory Template Starting Address Registers Section 13.6, “Programming the Logical Memory Attributes”...
Page 551 GLOSSARY...
Page 553 GLOSSARY Address Space An array of bytes used to store program code, data, stacks and system data structures required to execute a program. Address space is linear – also called flat – and byte addressable, with addresses running contigu- ously from 0 to 2 - 1.
Page 554 GLOSSARY Fault Table An architecture-defined data structure that contains pointers to fault handling procedures. Each fault table entry is associated with a particular fault type. When the processor generates a fault, it uses the fault table to select the proper fault handling procedure for the type of fault condition detected. Fault An event that the processor generates to indicate that, while executing the program, a condition arose that could cause the processor to go down a...
Page 555 GLOSSARY Instruction Cache A memory array used for temporary storage of instructions fetched from main memory. Its purpose is to streamline instruction execution by reducing the number of instruction fetches required to execute a program. Instruction Pointer A 32-bit register that contains the address (in the address space) of the (IP) instruction currently being executed.
Page 556 GLOSSARY Local Call A procedure call that does not require a switch in the current execution mode or a switch to another stack. Local calls can be made explicitly through the instructions and implicitly through the call callx calls fault call mechanism. Local Registers A set of 16 general-purpose data registers (r0 through r15) whose contents are associated with the procedure currently being executed.
Page 557 GLOSSARY PRCB See Process Control Block. Precise Faults Faults generated in the order in which they occur in the instruction stream and with sufficient fault information to allow software to recover from the faults without altering program’s control flow. The AC register NIF bit and the instruction allow software to force all faults to be precise.
Page 558 GLOSSARY See Return Instruction Pointer. Software Reset Re-running of the Reset microcode without physically asserting the RESET# pin or removing power from the CPU. See Stack Pointer. Special Function A 32-bit register (sf0-sf4) used to control specific sections of the Registers (SFRs) processor.
Page 559 GLOSSARY Supervisor Stack The address of the first byte of the supervisor stack. The supervisor stack Pointer pointer is contained in bytes 12 through 15 of the system procedure table and the trace table. Supervisor Stack The procedure stack that the processor uses when in supervisor mode. System Call An explicit procedure call made with the calls...
Page 560 GLOSSARY Tracing The ability of the processor to detect execution of certain instruction types, such as branch, call and return. When tracing is enabled, the processor generates a fault whenever it detects a trace event. A trace fault handler can then be designed to call a debug monitor to provide information on the trace event and its location in the instruction stream.
Page 561 INDEX...
Page 563 INDEX register indirect addressing registers and literals absolute alignment, registers and literals displacement addressing mode 6-12 alterbit memory addressing mode 6-13 offset addressing mode 6-13 andnot 3-18 12-9 architecture reserved memory space AC register, see Arithmetic Controls (AC) register 7-13 argument list access faults 3-18...
Page 564 INDEX big endian byte order resource request message D-10 big-endian byte order Breakpoint Control (BPCON) register selecting programming little endian byte order Breakpoint Control Register (BPCON) 13-12 6-23 selecting bswap 12-2 built-in self test bit definition 12-6 bus confidence self test 5-11 bit field instructions 13-6...
Page 565 INDEX return operation 6-25 3-24 calls cache call-trace mode data 6-27 callx cache coherency and non-cacheable accesses 3-19 carry conditions 6-29 described check bit instruction enabling and disabling 6-29 chkbit fill policy 6-30 clear bit instruction partial-hit multi-word data accesses 12-34 clock input (CLKIN) 4-10...
Page 566 INDEX 15-18 comparison instructions, overview timing diagram compare and increment or decrement instructions data structures 5-13 3-12 control table 5-13 test condition instructions 3-12 fault table 6-38 concmpi 3-11 Initialization Boot Record (IBR) 6-38 concmpo 3-12 interrupt stack 3-19 conditional branch instructions 3-12 interrupt table 5-17...
Page 567 INDEX system-supervisor calls user stack 6-48 ediv fault record 14-8 8-bit bus width byte enable encodings address-of-faulting-instruction field 14-13 8-bit wide data bus bursts fault subtype field 12-40 electromagnetic interference (EMI) location 12-40 electrostatic interference (ESI) structure 6-49 emul 3-12 fault table endianism 3-15...
Page 568 INDEX 6-55 3-11 12-1 fmark Initialization Boot Record (IBR) 12-13 12-15 6-55 force mark instruction 3-15 alignment FP, see Frame Pointer 3-11 initialization data structures frame fills initialization mechanism Frame Pointer (FP) initialization requirements location 12-9 architecture reserved memory space frame spills 12-21 D-22...
Page 569 INDEX 6-11 6-35 addo cmpibno 6-35 addoe cmpibo 6-32 addog cmpinci 6-32 addoge cmpinco 5-12 addol cmpis 5-12 6-33 addole cmpo 6-35 addone cmpobe 6-35 addono cmpobg 6-35 addoo cmpobge 6-12 6-35 alterbit cmpobl 6-13 6-35 cmpoble 6-13 6-35 andnot cmpobne 3-15 6-14...
Page 570 INDEX 6-70 6-104 3-16 stib 6-70 6-104 stis 6-74 6-104 3-15 mark 6-75 6-104 3-18 modac stob 6-76 modi stos 6-77 6-104 modify 3-16 6-78 6-104 modpc 3-21 3-22 3-23 6-80 6-108 modtc subc 6-81 6-112 subi 6-81 6-109 movl subie 6-81 6-109...
Page 571 INDEX 6-66 11-25 D-18 intctl 3-23 Interrupt Mask (IMSK) register 6-68 11-26 3-23 Interrupt Mask (IMSK) Registers intdis 5-23 11-25 integer flow masking Interrupt Pending (IPND) Register 11-25 integers Interrupt Pending (IPND) register data truncation atomic-read-modify-write sequence sign extension interrupt performance 6-69 11-36 inten...
Page 572 INDEX 11-31 interrupt handling procedures call 11-7 interrupt record callx 11-7 interrupt stack local register cache 11-4 3-17 interrupt table overview 11-18 masking hardware interrupts local registers 11-17 mixed mode allocation 11-3 11-8 Non-Maskable Interrupt (NMI) management 11-1 overview overview 11-18 physical characteristics usage...
Page 573 INDEX 3-14 external memory requirements NMI, see Non-Maskable Interrupt (NMI) 3-14 atomic access 8-15 8-20 No Imprecise Faults (AC.nif) bit 3-16 big endian byte order 11-3 11-8 Non-Maskable Interrupt (NMI) 3-15 data alignment 11-18 signal 3-15 data block sizes 6-86 3-16 data block storage 6-87...
Page 574 INDEX 11-27 location access 7-20 addressing 7-20 Previous Frame Pointer Register (PFP) (r0) addressing and alignment 11-3 11-18 priority-31 interrupts Breakpoint Control (BPCON) 3-17 procedure calls cache branch-and-link control memory-mapped call and return mechanism DEVICEID leaf procedures memory location procedure stack global growth indirect addressing mode...
Page 575 INDEX 3-23 Trace Controls (TC) Register Select Based on Unordered 6-120 registers select instructions 15-7 12-6 Boundary-Scan self test (STEST) pin 13-6 6-97 Bus Control (BCON) selg 12-22 D-23 6-97 device ID selge 15-5 6-97 Instruction sell 6-97 Interrupt Control (ICON) selle 6-97 Interrupt Map Control (IMAP0-IMAP2)
Page 576 INDEX 6-112 15-2 subi Test Access Port (TAP) controller 6-109 15-3 architecture subie 6-109 15-5 Asynchronous Reset Input (TRST) pin subig 6-109 15-3 block diagram subige 6-109 15-5 Serial Test Data Output (TDO) pin subil 6-109 15-4 subile state diagram 6-109 15-5 subine...
Page 577 INDEX mark fmark PC and TC registers trace-fault-pending flag 10-7 TRR), TRR1 3-19 true/false conditions 12-37 TTL input pins 14-14 two-word burst write transaction 3-19 unordered numbers 3-11 user space family registers and tables 3-12 7-19 user stack 3-15 alignment 3-23 user supervisor protection model 3-23...