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INSTRUCTION SET OVERVIEW
5.3.1.6
Simple Control Transfer
There is no branch lookahead or branch prediction mechanism on the i960 Jx processor. Simple
branch instructions take one cycle to execute, and one more cycle is needed to fetch the target
instruction when the branch is actually taken.
b, bal, bno, bo, bl, ble, be, bne, bg, bge
One mode of the
(branch-extended) instruction,
bx
cycle to execute and one cycle to fetch the target.
As a result, a
or
bal (g14)
bx (g14)
efficient leaf procedure implementation.
Compare-and-branch instructions have been optimized on the i960 Jx processor. They require 2
cycles to execute, and one more cycle to fetch the target instruction when the branch is actually
taken. The instructions are:
• cmpobno
• cmpobo
• cmpobg
• cmpobge
• cmpibe
• cmpibg
5.3.1.7
Memory Instructions
The i960 Jx processor provides efficient support for naturally aligned byte, short, and word
accesses that use one of 6 optimized addressing modes. These accesses require only 1 to 2 cycles
to execute; additional cycles are needed for a load to return its data.
The byte, short and word memory instructions are:
ldob, ldib, ldos, ldis, ld, lda stob, stib, stos, stis, st
The remainder of accesses require multiple cycles to execute. These include:
•
Unaligned short, and word accesses
•
Byte, short, and word accesses that do not use one of the 6 optimized addressing modes
•
Multi-word accesses
The multi-word accesses are:
ldl, ldt, ldq, stl, stt, stq
5-22
(base), is also a simple branch and takes one
bx
sequence provides a two-cycle call and return mechanism for
• cmpobl
• cmpoble
• cmpibno
• cmpibo
• cmpibne
• cmpibge
• cmpobe
• cmpobne
• cmpibl
• cmpible
• bbc
• bbs
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